HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 416
![MCU 5V 256K J-TEMP PB-FREE QFP-1](/photos/28/62/286212/168-bqfp_sml.jpg)
HD64F7051SFJ20V
Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet
1.HD64F7050SFJ20V.pdf
(843 pages)
Specifications of HD64F7051SFJ20V
Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 416 of 843
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Section 13 Serial Communication Interface (SCI)
13.3
13.3.1
For serial communication, the SCI has an asynchronous mode in which characters are
synchronized individually, and a clock synchronous mode in which communication is
synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission
format are selected in the serial mode register (SMR), as shown in table 13.8. The SCI clock
source is selected by the C/A bit in the serial mode register (SMR) and the CKE1 and CKE0 bits
in the serial control register (SCR), as shown in table 13.9.
Asynchronous Mode:
Clock Synchronous Mode:
Rev. 5.00 Jan 06, 2006 page 394 of 818
REJ09B0273-0500
Data length is selectable: seven or eight bits.
Parity and multiprocessor bits are selectable, as well as the stop bit length (one or two bits).
These selections determine the transmit/receive format and character length.
In receiving, it is possible to detect framing errors (FER), parity errors (PER), overrun errors
(ORER), and the break state.
An internal or external clock can be selected as the SCI clock source.
The communication format has a fixed 8-bit data length.
In receiving, it is possible to detect overrun errors (ORER).
An internal or external clock can be selected as the SCI clock source.
When an internal clock is selected, the SCI operates using the on-chip baud rate generator
clock, and can output a clock with a frequency matching the bit rate.
When an external clock is selected, the external clock input must have a frequency 16 times
the bit rate. (The on-chip baud rate generator is not used.)
When an internal clock is selected, the SCI operates using the on-chip baud rate generator
clock, and outputs a synchronous clock signal to external devices.
When an external clock is selected, the SCI operates on the input synchronous clock. The
on-chip baud rate generator is not used.
Operation
Overview
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