HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 250

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

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Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
Timer I/O Control Registers 1A to 1C and 2A (TIOR1A to TIOR1C, TIOR2A)
Timer I/O control register 1A to 1C and 2A (TIOR1A to TIOR1C, TIOR2A) are 8-bit registers.
There are four TIOR registers, three for timer 1 and one for timer 2.
Registers TIOR0A to TIOR1C specify whether general registers GR1A to GR1F are used as input
capture or compare-match registers, and also perform edge detection and output value setting.
Each TIOR is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
TIOR2A specifies whether general registers GR2A and GR2B are used as input capture or
compare-match registers, and also performs edge detection and output value setting.
Rev. 5.00 Jan 06, 2006 page 228 of 818
REJ09B0273-0500
Initial value:
Initial value:
Initial value:
Initial value:
TIOR1A
TIOR1B
TIOR1C
TIOR2A
R/W:
R/W:
R/W:
R/W:
Bit:
Bit:
Bit:
Bit:
R
R
R
R
7
0
7
0
7
0
7
0
IO1D2
IO1B2
IO1F2
IO2B2
R/W
R/W
R/W
R/W
6
0
6
0
6
0
6
0
IO1D1
IO1B1
IO1F1
IO2B1
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
IO1D0
IO1B0
IO1F0
IO2B0
R/W
R/W
R/W
R/W
4
0
4
0
4
0
4
0
R
R
R
R
3
0
3
0
3
0
3
0
IO1C2
IO1A2
IO1E2
IO2A2
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
IO1C1
IO1A1
IO1E1
IO2A1
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
IO1C0
IO1A0
IO1E0
IO2A0
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0

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