HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 111

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

6.4
6.4.1
The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest priority interrupt in the interrupt requests sent,
3. The interrupt controller compares the priority level of the selected interrupt request with the
4. When the interrupt controller accepts an interrupt, a low level is output from the IRQOUT pin.
5. The CPU detects the interrupt request sent from the interrupt controller when it decodes the
6. SR and PC are saved onto the stack.
7. The priority level of the accepted interrupt is copied to the interrupt mask level bits (I3 to I0) in
8. When the accepted interrupt is sensed by level or is from an on-chip peripheral module, a high
9. The CPU reads the start address of the exception service routine from the exception vector
following the priority levels set in interrupt priority level setting registers A–H (IPRA–IPRH).
Lower-priority interrupts are ignored. They are held pending until interrupt requests designated
as edge-detect type are accepted. For IRQ interrupts, however, withdrawal is possible by
accessing the IRQ status register (ISR). See section 6.2.3, IRQ Interrupts, for details. Interrupts
held pending due to edge detection are cleared by a power-on reset or a manual reset. If two of
these interrupts have the same priority level or if multiple interrupts occur within a single
module, the interrupt with the highest default priority or the highest priority within its IPR
setting range (as indicated in table 6.3) is selected.
interrupt mask bits (I3–I0) in the CPU’s status register (SR). If the request priority level is
equal to or less than the level set in I3–I0, the request is ignored. If the request priority level is
higher than the level in bits I3–I0, the interrupt controller accepts the interrupt and sends an
interrupt request signal to the CPU.
next instruction to be executed. Instead of executing the decoded instruction, the CPU starts
interrupt exception processing (figure 6.5).
the status register (SR).
level is output from the IRQOUT pin. When the accepted interrupt is sensed by edge, a high
level is output from the IRQOUT pin at the point when the CPU starts interrupt exception
processing instead of instruction execution as noted in (5) above. However, if the interrupt
controller accepts an interrupt with a higher priority than one it is in the midst of accepting, the
IRQOUT pin will remain low level.
table for the accepted interrupt, jumps to that address, and starts executing the program there.
This jump is not a delay branch.
Interrupt Sequence
Interrupt Operation
Rev. 5.00 Jan 06, 2006 page 89 of 818
Section 6 Interrupt Controller (INTC)
REJ09B0273-0500