HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 265

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit 0—Input Capture/Compare-Match Flag (IMF2A): Status flag that indicates GR2A input
capture or compare-match.
Timer Status Registers DH and DL (TSRDH, TSRDL)
TSRDH indicates the status of channel 3 input capture, compare-match, and overflow.
Note:
Bits 7 to 5—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 4—Overflow Flag (OVF3): Status flag that indicates TCNT3 overflow.
Bit 0:
IMF2A
0
1
Bit 4:
OVF3
0
1
Initial value:
* Only 0 can be written, to clear the flag.
Description
[Clearing condition]
When IMF2A is read while set to 1, then 0 is written in IMF2A
[Setting conditions]
Description
[Clearing condition]
When OVF3 is read while set to 1, then 0 is written in OVF3
[Setting condition]
When the TCNT3 value overflows (from H'FFFF to H'0000)
R/W:
Bit:
When the TCNT2 value is transferred to GR2A by an input capture signal while
GR2A is functioning as an input capture register
When TCNT2 = GR2A while GR2A is functioning as an output compare register
—
R
7
0
—
R
6
0
—
R
5
0
R/(W) *
OVF3
4
0
Rev. 5.00 Jan 06, 2006 page 243 of 818
Section 10 Advanced Timer Unit (ATU)
R/(W) *
IMF3D
3
0
R/(W) *
IMF3C
2
0
REJ09B0273-0500
R/(W) *
IMF3B
1
0
(Initial value)
(Initial value)
R/(W) *
IMF3A
0
0