HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 668

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 21 Power-Down State
21.3
21.3.1
The chip enters hardware standby mode when the HSTBY pin goes low. Hardware standby mode
reduces power consumption drastically by halting all chip functions. As the transition to hardware
standby mode is made by means of external pin input, the transition is made asynchronously,
regardless of the current state of the chip, and therefore the chip state prior to the transition is not
preserved. However, on-chip RAM data is retained as long as the specified voltage is supplied. To
retain on-chip RAM data, clear the RAM enable bit (RAME) to 0 in the system control register
(SYSCR) before driving the HSTBY pin low. See “Pin States” for the pin states in hardware
standby mode.
21.3.2
Hardware standby mode is exited by means of the HSTBY pin and RES pin. When HSTBY is
driven high while RES is low, the clock oscillator starts running. The RES pin should be held low
long enough for clock oscillation to stabilize. When RES is driven high, power-on reset exception
handling is started and a transition is made to the program execution state.
21.3.3
Figure 21.1 shows sample pin timings for hardware standby mode. A transition to hardware
standby mode is made by driving the HSTBY pin low after driving the RES pin low. Hardware
standby mode is exited by driving HSTBY high, waiting for clock oscillation to stabilize, then
switching RES from low to high.
Rev. 5.00 Jan 06, 2006 page 646 of 818
REJ09B0273-0500
Transition to Hardware Standby Mode
Exit from Hardware Standby Mode
Hardware Standby Mode Timing
Hardware Standby Mode