HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 179

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 9.4 shows the example of changes in priority levels when transfer requests are issued
simultaneously for channels 0 and 3, and channel 1 receives a transfer request during a transfer on
channel 0. The DMAC operates in the following manner under these circumstances:
1. Transfer requests are issued simultaneously for channels 0 and 3.
2. Since channel 0 has a higher priority level than channel 3, the channel 0 transfer is conducted
3. A transfer request is issued for channel 1 during a transfer on channel 0 (channels 1 and 3 are
4. At the end of the channel 0 transfer, channel 0 shifts to the lowest priority level.
5. At this point, channel 1 has a higher priority level than channel 3, so the channel 1 transfer
6. When the channel 1 transfer ends, channel 1 shifts to the lowest priority level.
7. Channel 3 transfer begins.
8. When the channel 3 transfer ends, channel 3 and channel 2 priority levels are lowered, giving
Transfer request
Issued for
Issued for channel 1
first (channel 3 is on transfer standby).
on transfer standby).
comes first (channel 3 is on transfer standby).
channel 3 the lowest priority.
channels 0 and 3
Figure 9.4 Example of Changes in Priority in Round Robin Mode
Channel waiting
1.3
3
3
None
DMAC operation
Channel 0
transfer begins
Channel 0
transfer ends
Channel 1
transfer begins
Channel 1
transfer ends
Channel 3
transfer begins
Channel 3
transfer ends
Section 9 Direct Memory Access Controller (DMAC)
Rev. 5.00 Jan 06, 2006 page 157 of 818
Change of
priority
Change of
priority
Change of
priority
Channel priority
0
1
2
0
REJ09B0273-0500
1
2
3
1
2
3
0
2
3
0
1
3