HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 170

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
HD64F7051SFJ20V
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Section 9 Direct Memory Access Controller (DMAC)
Bit 0—DMAC Enable (DE): DE enables operation in the corresponding channel.
Bit 0: DE
0
1
Transfer mode is entered if this bit is set to 1 when auto-request is specified (RS3–RS0 settings).
With an external request or on-chip module request, when a transfer request occurs after this bit is
set to 1, transfer is enabled. If this bit is cleared during a data transfer, transfer is suspended.
If the DE bit has been set, but TE = 1, then if the DME bit of the DMAOR is 0, and the NMI or
AE bit of the DMAOR is 1, transfer enable mode is not entered.
9.2.5
The DMAOR is a 16-bit read/write register that specifies the transfer mode of the DMAC. Bits
15–10 and bits 7–3 of this register always read as 0 and cannot be modified.
Register values are initialized to 0 by a power-on reset and in software standby mode.
Note:
Rev. 5.00 Jan 06, 2006 page 148 of 818
REJ09B0273-0500
Initial value:
Initial value:
* 0 write only is valid after 1 is read at the AE and NMIF bits.
DMAC Operation Register (DMAOR)
R/W:
R/W:
Bit:
Bit:
15
R
R
0
7
0
Description
Operation of the corresponding channel disabled (initial value)
Operation of the corresponding channel enabled
14
R
R
0
6
0
13
R
R
0
5
0
12
R
R
0
4
0
11
R
R
0
3
0
R/(W) *
AE
10
R
0
2
0
R/(W) *
NMIF
PR1
R/W
9
0
1
0
DME
PR0
R/W
R
8
0
0
0

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