HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 44

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 2 CPU
2.1.2
The 32-bit control registers consist of the 32-bit status register (SR), global base register (GBR),
and vector base register (VBR). The status register indicates processing states. The global base
register functions as a base address for the indirect GBR addressing mode to transfer data to the
registers of on-chip peripheral modules. The vector base register functions as the base address of
the exception processing vector area (including interrupts). Figure 2.2 shows a control register.
Rev. 5.00 Jan 06, 2006 page 22 of 818
REJ09B0273-0500
SR
31
31
31
Control Registers
M Q I3 I2 I1 I0
9 8 7 6 5 4 3 2 1 0
GBR
VBR
Figure 2.2 Control Register Configuration
S T
0
0
SR: Status register
T bit: The MOVT, CMP/cond, TAS, TST,
S bit: Used by the MAC instruction.
Reserved bits. This bit always read 0.
The write value should always be 0.
Bits I0–I3: Interrupt mask bits.
M and Q bits: Used by the DIV0U, DIV0S,
Reserved bits. 0 is read. Write only.
Global base register (GBR):
Indicates the base address of the indirect
GBR addressing mode. The indirect GBR
addressing mode is used in data transfer
for on-chip peripheral modules register
areas and in logic operations.
Vector base register (VBR):
Stores the base address of the exception
processing vector area.
BT (BT/S), BF (BF/S), SETT, and CLRT
instructions use the T bit to indicate true
(1) or false (0). The ADDV, ADDC,
SUBV, SUBC, DIV0U, DIV0S, DIV1,
NEGC, SHAR, SHAL, SHLR, SHLL,
ROTR, ROTL, ROTCR, and ROTCL
instructions also use the T bit to indicate
carry/borrow or overflow/underflow.
and DIV1 instructions.