HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 311
![MCU 5V 256K J-TEMP PB-FREE QFP-1](/photos/28/62/286212/168-bqfp_sml.jpg)
HD64F7051SFJ20V
Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet
1.HD64F7050SFJ20V.pdf
(843 pages)
Specifications of HD64F7051SFJ20V
Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 311 of 843
- Download datasheet (5Mb)
Section 10 Advanced Timer Unit (ATU)
10.3.5
One-Shot Pulse Function
ATU channel 10 has eight down-counters (DCNT10A to DCNT10H) and corresponding external
pins (TOA10 to TOH10) which can be used as one-shot pulse output pins.
To generate a one-shot pulse, the one-shot pulse width is set in the down-counter (DCNT), and the
corresponding down-count start register (DSTR) bit (DST10A to DST10H) is set to 1 by the user
program to start the down-count using the clock specified in the timer control register (TCR).
When the down-count starts, 1 is output to the corresponding external pin (TOA10 to TOH10). If
the DCNT value is 0, however, the external pin remains at 0 even if DST is set to 1; in this case, a
one-shot pulse is not generated, but an interrupt is requested. When the DCNT value underflows,
DCNT and the relevant DST bit are automatically cleared to 0, and DCNT stops counting. At the
same time, 0 is output to the corresponding external pin.
By making the appropriate setting in timer interrupt enable register F (TIERF), an interrupt request
can be sent to the CPU when the corresponding down-counter (DCNT10A to DCNT10H) reaches
0.
It is possible to forcibly output 0 to the output pin during the down-count by clearing DCNT to 0
(since DST cannot be cleared to 0 by the user program). In this case, DCNT and the relevant DST
bit are automatically cleared to 0 when the DCNT value underflows, and DCNT stops counting.
At the same time, 0 is output to the corresponding external pin.
An example of one-shot pulse operation is shown in figure 10.15.
In the example in figure 10.15, one-shot pulse widths dataA and dataB are set for DCNT10A by
the user program, and one-shot pulse output is performed by writing 1 to DST10A.
Rev. 5.00 Jan 06, 2006 page 289 of 818
REJ09B0273-0500
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