HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 635

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.7.3
When erasing flash memory, the erase/erase-verify flowchart shown in figure 19.8 should be
followed.
To perform data or program erasure, set the flash memory area to be erased in erase block register
n (EBRn) at least 10 µs after setting the SWE bit to 1 in flash memory control register 1
(FLMCR1). Next, the watchdog timer is set to prevent overerasing in the event of program
runaway, etc. Set 6.6 ms as the WDT overflow period. After this, preparation for erase mode
(erase setup) is carried out by setting the ESUn bit in FLMCRn, and after the elapse of 200 µs or
more, the operating mode is switched to erase mode by setting the En bit in FLMCRn. The time
during which the En bit is set is the flash memory erase time. Ensure that the erase time does not
exceed 5 ms.
Note: With flash memory erasing, preprogramming (setting all memory data in the memory to
19.7.4
In erase-verify mode, data is read after memory has been erased to check whether it has been
correctly erased.
After the elapse of a the erase time, erase mode is exited (the En bit in FLMCRn is cleared, then
the ESUn bit is cleared at least 10 µs later), the watchdog timer is cleared after the elapse of 10 µs
or more, and the operating mode is switched to erase-verify mode by setting the EVn bit in
FLMCRn. Before reading in erase-verify mode, a dummy write of H'FF data should be made to
the addresses to be read. The dummy write should be executed after the elapse of 20 µs or more.
When the flash memory is read in this state (verify data is read in 32-bit units), the data at the
latched address is read. Wait at least 2 µs after the dummy write before performing this read
operation. If the read data has been erased (all “1”), a dummy write is performed to the next
address, and erase-verify is performed. The erase-verify operation is carried out on all the erase
blocks; the erase block register bit for an erased block should be cleared to prevent excessive
application of the erase voltage. When verification is completed, exit erase-verify mode, and wait
for at least 5 µs. If erasure has been completed on all the erase blocks after completing erase-verify
operations on all these blocks, clear the SWE bit in FLMCR1. If there are any unerased blocks, set
erase mode again, and repeat the erase/erase-verify sequence as before. However, ensure that the
erase/erase-verify sequence is not repeated more than 60 times.
be erased to all “0”) is not necessary before starting the erase procedure.
Erase Mode (n = 1 for Addresses H'0000 to H'1FFFF, n = 2 for Addresses H'20000
to H'3FFFF)
Erase-Verify Mode (n = 1 for Addresses H'0000 to H'1FFFF, n = 2 for Addresses
H'20000 to H'3FFFF)
Rev. 5.00 Jan 06, 2006 page 613 of 818
Section 19 ROM (256 kB Version)
REJ09B0273-0500