HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 538

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 16 Pin Function Controller (PFC)
16.3.15 CK Control Register (CKCR)
CK control register (CKCR) is a 16-bit readable/writable register being used for controlling clock
output from CK terminal.
CKCR is initialized to H'FFFE by a power-on reset and in hardware standby mode. It is not
initialized in software standby mode or sleep mode.
Bits 15 to 1—Reserved: This bit is always read as 1, and should only be written with 1.
Bit 0—CK low fixed bit (CKLO): This bit is used for selecting the internal clock output or low
level output for output from the CK terminal.
Bit 0:
CKLO
0
1
Rev. 5.00 Jan 06, 2006 page 516 of 818
REJ09B0273-0500
Initial value:
R/W:
Bit:
Description
Selects the internal clock for the CK terminal output
Always selects the low level for the CK terminal output
15
R
1
14
R
1
13
R
1
12
R
1
11
R
1
10
R
1
R
9
1
R
8
1
R
7
1
R
6
1
R
5
1
R
4
1
R
3
1
R
2
1
(Initial value)
R
1
1
CKLO
R/W
0
0

Related parts for HD64F7051SFJ20V