HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 506

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 16 Pin Function Controller (PFC)
16.3.3
The port B IO register (PBIOR) is a 16-bit readable/writable register that selects the input/output
direction of the 12 pins in port B. Bits PB11IOR to PB0IOR correspond to pins PB11/A21/POD to
PB0/TO6. PBIOR is enabled when port B pins function as general input/output pins (PB11 to
PB0), and disabled otherwise. PBIOR bits 4 and 5 should be cleared to 0 when ATU clock input is
selected.
When port B pins function as PB11 to PB0, a pin becomes an output when the corresponding bit
in PBIOR is set to 1, and an input when the bit is cleared to 0.
PBIOR is initialized to H'C0C0 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
16.3.4
The port B control register (PBCR) is a 16-bit readable/writable register that selects the functions
of the 12 multiplex pins in port B.
PBCR is initialized to H'80C0 by a power-on reset (excluding a WDT power-on reset), and in
hardware standby mode. It is not initialized in software standby mode or sleep mode.
Bit 15—Reserved: This bit is always read as 1, and should only be written with 1.
Rev. 5.00 Jan 06, 2006 page 484 of 818
REJ09B0273-0500
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
Port B IO Register (PBIOR)
Port B Control Register (PBCR)
15
15
—
—
R
R
1
1
PB11
R/W R/W R/W R/W R/W R/W R/W
MD1
14
14
—
R
1
0
PB11
PB11
R/W R/W R/W R/W R/W R/W
MD0
IOR
13
13
0
0
PB10
PB10
IOR
MD
12
12
0
0
PB9
PB9
IOR
MD
11
11
0
0
PB8
PB8
IOR
MD
10
10
0
0
PB7
PB7
IOR
MD
9
0
9
0
PB6
PB6
IOR
MD
8
0
8
0
—
—
R
R
7
1
7
1
—
—
R
R
6
1
6
1
R/W R/W R/W R/W R/W R/W
R/W R/W R/W R/W R/W R/W
PB5
PB5
IOR
MD
5
0
5
0
PB4
PB4
IOR
MD
4
0
4
0
PB3
PB3
IOR
MD
3
0
3
0
PB2
PB2
IOR
MD
2
0
2
0
PB1
PB1
IOR
MD
1
0
1
0
PB0
PB0
IOR
MD
0
0
0
0