HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 486

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 15 Compare Match Timer (CMT)
Bits 1, 0—Clock Select 1, 0 (CKS1, CKS0): These bits select the clock input to the CMCNT
from among the four internal clocks obtained by dividing the system clock ( ). When the STR bit
of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and
CKS0.
Bit 1: CKS1
0
1
15.2.3
The compare match timer counter (CMCNT) is a 16-bit register used as an upcounter for
generating interrupt requests.
When an internal clock is selected with the CKS1, CKS0 bits of the CMCSR register and the STR
bit of the CMSTR is set to 1, the CMCNT begins incrementing with that clock. When the CMCNT
value matches that of the compare match timer constant register (CMCOR), the CMCNT is
cleared to H'0000 and the CMF flag of the CMCSR is set to 1. If the CMIE bit of the CMCSR is
set to 1 at this time, a compare match interrupt (CMI) is requested.
The CMCNT is initialized to H'0000 by a power-on reset and in hardware standby mode and
software standby mode.
Rev. 5.00 Jan 06, 2006 page 464 of 818
REJ09B0273-0500
Initial value:
Initial value:
Compare Match Timer Counter (CMCNT)
R/W:
R/W:
Bit:
Bit:
Bit 0: CKS0
0
1
0
1
R/W
R/W
15
0
7
0
R/W
R/W
14
0
6
0
Description
/8 (initial status)
/32
/128
/512
R/W
R/W
13
0
5
0
R/W
R/W
12
0
4
0
R/W
R/W
11
0
3
0
R/W
R/W
10
0
2
0
R/W
R/W
9
0
1
0
R/W
R/W
8
0
0
0

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