HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 748

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix A On-Chip Supporting Module Registers
Timer Status Register B (TSRB)
Note:
Bit
6
5
4
3
Rev. 5.00 Jan 06, 2006 page 726 of 818
REJ09B0273-0500
Initial value:
* Only 0 can be written to clear the flag.
Bit name:
Bit Name
Overflow flag
(OVF1)
Input capture/
compare match flag
(IMF1F)
Input capture/
compare match flag
(IMF1E)
Input capture/
compare match flag
(IMF1D)
R/W:
Bit:
—
R
7
0
R/(W) *
OVF1
Value
0
1
0
1
0
1
0
1
6
0
R/(W) *
IMF1F
Description
[Clearing condition]
Read OVF1 when OVF1 =1, then write 0 in OVF1
[Setting condition]
TCNT1 overflowed from H'FFFF to H'0000
[Clearing condition]
Read IMF1F when IMF1F =1, then write 0 in IMF1F
[Setting conditions]
1. TCNT1 value is transferred to GR1F by an input
2. TCNT1 = GR1F when GR1F functions as an output
[Clearing condition]
Read IMF1E when IMF1E =1, then write 0 in IMF1E
[Setting conditions]
1. TCNT1 value is transferred to GR1E by an input
2. TCNT1 = GR1E when GR1E functions as an output
[Clearing condition]
Read IMF1D when IMF1D =1, then write 0 in IMF1D
[Setting conditions]
1. TCNT1 value is transferred to GR1D by an input
2. TCNT1 = GR1D when GR1D functions as an output
5
0
H'FFFF82C5 (Channel 1)
capture signal when GR1F functions as an input
capture register
compare register
capture signal when GR1E functions as an input
capture register
compare register
capture signal when GR1D functions as an input
capture register
compare register
R/(W) *
IMF1E
4
0
R/(W) *
IMF1D
3
0
R/(W) *
IMF1C
2
0
8
R/(W) *
IMF1B
1
0
(Initial value)
(Initial value)
(Initial value)
(Initial value)
R/(W) *
IMF1A
ATU
0
0