HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 101

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

In IRQ interrupt exception processing, the interrupt mask bits (I3–I0) of the status register (SR)
are set to the priority level value of the accepted IRQ interrupt.
6.2.4
On-chip peripheral module interrupts are interrupts generated by the following on-chip peripheral
modules:
A different interrupt vector is assigned to each interrupt source, so the exception service routine
does not have to decide which interrupt has occurred. Priority levels between 0 and 15 can be
assigned to individual on-chip peripheral modules in interrupt priority registers C–H (IPRC–
IPRH).
On-chip peripheral module interrupt exception processing sets the interrupt mask level bits (I3–I0)
in the status register (SR) to the priority level value of the on-chip peripheral module interrupt that
was accepted.
6.2.5
Table 6.3 lists interrupt sources and their vector numbers, vector table address offsets and interrupt
priorities.
Each interrupt source is allocated a different vector number and vector table address offset. Vector
table addresses are calculated from vector numbers and address offsets. In interrupt exception
processing, the exception service routine start address is fetched from the vector table indicated by
the vector table address. See table 5.4, Calculating Exception Processing Vector Table Addresses.
IRQ interrupts and on-chip peripheral module interrupt priorities can be set freely between 0 and
15 for each pin or module by setting interrupt priority registers A–H (IPRA–IPRH). The ranking
of interrupt sources for IPRC–IPRH, however, must be the order listed under Priority within IPR
Setting Range in table 6.3 and cannot be changed. A power-on reset assigns priority level 0 to IRQ
interrupts and on-chip peripheral module interrupts. If the same priority level is assigned to two or
Direct memory access controller (DMAC)
Advanced timer unit (ATU)
Compare match timer (CMT)
A/D converter (A/D)
Serial communications interface (SCI)
Watchdog timer (WDT)
On-Chip Peripheral Module Interrupts
Interrupt Exception Vectors and Priority Rankings
Rev. 5.00 Jan 06, 2006 page 79 of 818
Section 6 Interrupt Controller (INTC)
REJ09B0273-0500