HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 32

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 1 Overview
Type
Clock
System
control
Operating
mode control
Interrupts
Rev. 5.00 Jan 06, 2006 page 10 of 818
REJ09B0273-0500
Symbol
EXTAL
XTAL
CK
RES
WDTOVF
BREQ
BACK
MD0 to
MD3
HSTBY
NMI
IRQ0 to
IRQ7
Pin No.
110
108
125
126
51
135
134
120, 119,
111, 109
124
112
106, 114,
116, 117, 6,
8, 54, 133
I/O
Input
Input
Output
Input
Output
Input
Output
Input
Input
Input
Input
Name
External clock
Crystal
System clock
Power-on
reset
Watchdog
timer overflow
Bus request
Bus request
acknowledge
Mode setting
Hardware
standby
Nonmaskable
interrupt
Interrupt
requests
0 to 7
Function
For connection to a crystal
resonator. An external clock
source can also be
connected to the EXTAL pin.
For connection to a crystal
resonator.
Supplies the system clock to
peripheral devices.
Executes a power-on reset
when driven low.
WDT overflow output signal.
Driven low when an external
device requests the bus.
Indicates that the bus has
been granted to an external
device. The device that
output the BREQ signal
recognizes that the bus has
been acquired when it
receives the BACK signal.
These pins determine the
operating mode. Do not
change the input values
during operation.
When driven low, this pin
forces a transition to
hardware standby mode.
Nonmaskable interrupt
request pin.
Acceptance on the rising
edge or falling edge can be
selected.
Maskable interrupt request
pins.
Level input or edge input can
be selected.