HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 288

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Advanced Timer Unit (ATU)
Bit 3—Interval Interrupt Bit 3 (ITVE3): Interrupt controller (INTC) interval interrupt setting
bit corresponding to bit 13 in TCNT0L. The rise of bit 13 in TCNT0L is ANDed with ITVE3, the
result is stored in IIF3 in the timer status register (TSRAH), and an interrupt request is sent to
INTC.
Bit 3:
ITVE3
0
1
Bit 2—Interval Interrupt Bit 2 (ITVE2): INTC interval interrupt setting bit corresponding to bit
12 in TCNT0L. The rise of bit 12 in TCNT0L is ANDed with ITVE2, the result is stored in IIF2 in
TSRAH, and an interrupt request is sent to INTC.
Bit 2:
ITVE2
0
1
Bit 1—Interval Interrupt Bit 1 (ITVE1): INTC interval interrupt setting bit corresponding to bit
11 in TCNT0L. The rise of bit 11 in TCNT0L is ANDed with ITVE1, the result is stored in IIF1 in
TSRAH, and an interrupt request is sent to INTC.
Bit 1
ITVE1
0
1
Bit 0—Interval Interrupt Bit 0 (ITVE0): INTC interval interrupt setting bit corresponding to bit
10 in TCNT0L. The rise of bit 10 in TCNT0L is ANDed with ITVE0, the result is stored in IIF0 in
TSRAH, and an interrupt request is sent to INTC.
Bit 0:
ITVE0
0
1
For details, see section 10.3.7, Interval Timer Operation.
Rev. 5.00 Jan 06, 2006 page 266 of 818
REJ09B0273-0500
Description
ATU interval interrupt generation is disabled
Generation of interval interrupt to INTC is enabled
Description
ATU interval interrupt generation is disabled
Generation of interval interrupt to INTC is enabled
Description
ATU interval interrupt generation is disabled
Generation of interval interrupt to INTC is enabled
Description
ATU interval interrupt generation is disabled
Generation of interval interrupt to INTC is enabled
(Initial value)
(Initial value)
(Initial value)
(Initial value)