HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 224

MCU 5V 256K J-TEMP PB-FREE QFP-1

HD64F7051SFJ20V

Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet

Specifications of HD64F7051SFJ20V

Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
Section 10 Advanced Timer Unit (ATU)
Block Diagram of Channel 1: Figure 10.3 shows a block diagram of ATU channel 1.
Rev. 5.00 Jan 06, 2006 page 202 of 818
REJ09B0273-0500
Legend:
TSTR:
TCR1:
TIOR1: Timer I/O control register 1 (8 bits)
TSRB:
Interrupts:
OVI1:
IMI1:
Inter-channel connection signals:
OFF1:
TRG0A: Channel 0/ICR0A input signal
TRG1A: Channel 1/GR1A compare-match signal
1
0
TCLKA
TCLKB
/(m·2
TSTR
m
n
n
)
5
32
Timer start register (16 bits)
Timer control register 1 (8 bits)
Timer status register B (8 bits)
Overflow interrupt 1
Input capture/compare-match interrupt 1
Offset compare-match signal
Clock selection
Figure 10.3 Block Diagram of Channel 1
Module data bus
Control logic
TIERB: Timer interrupt enable register B (8 bits)
TCNT1: Free-running counter 1 (16 bits)
GR1:
OSBR: Offset base register (16 bits)
General register 1 (16 bits)
Comparator
OFF1A–1F
OVI1
IMIA
IMIB
IMIC
IMID
IMIE
IMIF
TIOA1
TIOB1
TIOC1
TIOD1
TIOE1
TIOF1
TRG0A
TRG1A

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