HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 347

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Sample Setup Procedure for PWM Timer Operation (Channels 3 to 5 ): An example of the
setup procedure for PWM timer operation (channels 3 to 5 ) is shown in figure 10.51.
1. Set the first-stage counter clock ' in prescaler register 1 (PSCR1), and select the second-stage
2. Set the port E control register (PECR) or port G control register (PGCR), corresponding to the
3. Set bit T3PWM–T5PWM in the timer mode register (TMDR) to PWM mode. When PWM
4. The GR3A–GR3C, GR4A–GR4C, and GR5A ATU general registers are used as duty registers
5. Set the corresponding bit to 1 in the timer start register (TSTR) to start the free-running
counter clock " with the CKSEL bit in the timer control register (TCR). When selecting an
external clock, at the same time select the external clock edge type with the CKEG bit in TCR.
waveform output port, to ATU output compare-match output. Also set the corresponding bit to
1 in the port E IO register (PEIOR) or port G IO register (PGIOR) to specify the output
attribute.
mode is set, the TIOD3. TIOD4, and TIOD5 pins go to 0 output irrespective of the timer I/O
control register (TIOR) contents.
(DTR), and the GR3D, GR4D, and GR5B ATU general registers as cycle registers (CYLR).
Set the PWM waveform output 0 output timing in DTR, and the PWM waveform output 1
output timing in CYLR.
counter (TCNT) for the relevant channel.
Rev. 5.00 Jan 06, 2006 page 325 of 818
Section 10 Advanced Timer Unit (ATU)
REJ09B0273-0500