HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 16

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.3 Operation .......................................................................................................................... 394
13.4 SCI Interrupt Sources and the DMAC .............................................................................. 425
13.5 Notes on Use ..................................................................................................................... 426
Section 14 A/D Converter
14.1 Overview........................................................................................................................... 431
14.2 Register Descriptions ........................................................................................................ 437
14.3 CPU Interface.................................................................................................................... 447
14.4 Operation .......................................................................................................................... 448
Rev. 5.00 Jan 06, 2006 page xiv of xx
13.2.7 Serial Status Register (SSR) ................................................................................ 380
13.2.8 Bit Rate Register (BRR) ...................................................................................... 384
13.3.1 Overview.............................................................................................................. 394
13.3.2 Operation in Asynchronous Mode ....................................................................... 396
13.3.3 Multiprocessor Communication........................................................................... 406
13.3.4 Clock Synchronous Operation ............................................................................. 414
13.5.1 TDR Write and TDRE Flags................................................................................ 426
13.5.2 Simultaneous Multiple Receive Errors ................................................................ 426
13.5.3 Break Detection and Processing .......................................................................... 427
13.5.4 Sending a Break Signal........................................................................................ 427
13.5.5 Receive Error Flags and Transmitter Operation
13.5.6 Receive Data Sampling Timing and Receive Margin in the Asynchronous
13.5.7 Constraints on DMAC Use .................................................................................. 429
13.5.8 Cautions for Clock Synchronous External Clock Mode ...................................... 429
13.5.9 Caution for Clock Synchronous Internal Clock Mode......................................... 429
14.1.1 Features................................................................................................................ 431
14.1.2 Block Diagram ..................................................................................................... 432
14.1.3 Pin Configuration................................................................................................. 434
14.1.4 Register Configuration......................................................................................... 436
14.2.1 A/D Data Registers 0 to 15 (ADDR0 to ADDR15) ............................................. 437
14.2.2 A/D Control/Status Register 0 (ADCSR0)........................................................... 438
14.2.3 A/D Control Register 0 (ADCR0)........................................................................ 442
14.2.4 A/D Control/Status Register 1 (ADCSR1)........................................................... 444
14.2.5 A/D Control Register 1 (ADCR1)........................................................................ 445
14.2.6 A/D Trigger Register (ADTRGR) ....................................................................... 446
14.4.1 Single Mode......................................................................................................... 448
14.4.2 Scan Mode ........................................................................................................... 450
14.4.3 Analog Input Setting and A/D Conversion Time................................................. 452
14.4.4 External Triggering of A/D Conversion .............................................................. 454
14.4.5 A/D Converter Activation by ATU...................................................................... 455
(Clock Synchronous Mode Only) ........................................................................ 427
Mode .................................................................................................................... 427
................................................................................................. 431