HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 274

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 10 Advanced Timer Unit (ATU)
Bit 0—One-Shot Pulse Flag (OSF10A): Status flag that indicates a DCNT10A one-shot pulse.
Bit 0:
OSF10A
0
1
10.2.8
The timer interrupt enable registers (TIER) are 8-bit registers. The ATU has seven TIER registers:
one each for channels 0, 1, and 2, two for channels 3 to 5, one for channels 6 to 9, and one for
channel 10.
Channel
0
1
2
3
4
5
6
7
8
9
10
The TIER registers are 8-bit readable/writable registers that control enabling/disabling of free-
running counter (TCNT) overflow interrupt requests, channel 0 input capture interrupt requests,
interval interrupt requests, general register and dedicated input capture register input
capture/compare-match interrupt requests, channel 6 to 9 compare-match interrupt requests, and
down-counter (DCNT) underflow interrupt requests.
Each TIER is initialized to H'00 by a power-on reset, and in hardware standby mode and software
standby mode.
Rev. 5.00 Jan 06, 2006 page 252 of 818
REJ09B0273-0500
Timer Interrupt Enable Registers (TIER)
Description
[Clearing condition]
When OSF10A is read while set to 1, then 0 is written in OSF10A
[Setting condition]
When the down-counter (DCNT10A) value underflows
Abbreviation
TIERA
TIERB
TIERC
TIERDH,
TIERDL
TIERE
TIERF
Function
Controls input capture, compare-match, and interval interrupt
request enabling/disabling.
Controls input capture, compare-match, and overflow interrupt
request enabling/disabling.
Controls input capture, compare-match, and overflow interrupt
request enabling/disabling.
Controls cycle register compare-match interrupt request
enabling/disabling.
Controls underflow interrupt request enabling/disabling.
(Initial value)