UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 1006

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
2nd Edition
Edition
Modification of Caution in Figure 14-67 Flowchart of Slave
Transmission/Reception (in Continuous Transmission/Reception Mode)
Modification of Caution in Figure 14-69 Initial Setting Procedure for UART
Transmission
Modification of Caution in Figure 14-73 Flowchart of UART Transmission (in
Single-Transmission Mode)
Modification of Caution in Figure 14-75 Flowchart of UART Transmission (in
Continuous Transmission Mode)
Modification of Caution in Figure 14-77 Initial Setting Procedure for UART
Reception
Modification of Caution in Figure 14-81 Flowchart of UART Reception
Modification of Caution in Figure 14-89 Initial Setting Procedure for Address
Field Transmission
Modification of Figure 15-5 Format of Peripheral Enable Register 0 (PER0)
Addition of 15.4.2 Setting transfer clock by using IICWL and IICWH registers
Addition of Caution to 15.5.7 Canceling wait
Modification of Table 15-3 Bit Definitions of Main Extension Code
Modification of Figure 15-23 Flow When Setting WUP = 0 upon Address Match
(Including Extension Code Reception) to Figure 15-25 When Operating as Slave
Device after Releasing STOP Mode other than by INTIICA (When Not Required
to Operate as Master Device)
Modification of Figure 15-33 Example of Master to Slave Communication and
Figure 15-34 Example of Slave to Master Communication
Modification of Figure 16-1 Block Diagram of LCD Controller/Driver
Modification of Figure 16-5 Format of LCD boost level control register (VLCD)
Addition of Caution 1 to Figure 16-7 Format of Segment Enable Register
(SEGEN)
Modification of Figure 16-33 Examples of LCD Drive Power Connections
(Internal Voltage Boosting Method)
Modification of Figure 17-4 Format of Multiplication/Division Data Register C
(MDCH, MDCL)
Modification of Table 18-2 Response Time of DMA Transfer
Modification of Maskable interrupts
Modification of Table 19-1 Interrupt Source List
Modification of Figure 19-1 Basic Configuration of Interrupt Function
Modification of Table 19-2 Flags Corresponding to Interrupt Request Sources
Modification of Figure 19-2 Format of Interrupt Request Flag Registers (IF0L,
IF0H, IF1L, IF1H, IF2L, IF2H) (78K0R/LF3) to Figure 19-4 Format of Interrupt
Request Flag Registers (IF0L, IF0H, IF1L, IF1H, IF2L, IF2H) (78K0R/LH3)
Modification of Figure 19-5 Format of Interrupt Mask Flag Registers (MK0L,
MK0H, MK1L, MK1H, MK2L, MK2H) (78K0R/LF3) to Figure 19-7 Format of
Interrupt Mask Flag Registers (MK0L, MK0H, MK1L, MK1H, MK2L, MK2H)
(78K0R/LH3)
Modification of Figure 19-8 Format of Priority Specification Flag Registers
(PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H, PR11L, PR11H,
PR12L, PR12H) (78K0R/LF3) to Figure 19-10 Format of Priority Specification
Flag Registers (PR00L, PR00H, PR01L, PR01H, PR02L, PR02H, PR10L, PR10H,
PR11L, PR11H, PR12L, PR12H) (78K0R/LH3)
Description
APPENDIX D REVISION HISTORY
CHAPTER 14 SERIAL
ARRAY UNIT
(continuation)
CHAPTER 15 SERIAL
INTERFACE IICA
CHAPTER 16 LCD
CONTROLLER/DRIVER
CHAPTER 17
MULTIPLIER/DIVIDER
CHAPTER 18 DMA
CONTROLLER
CHAPTER 19
INTERRUPT
FUNCTIONS
Chapter
(4/11)
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