UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 746

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
19.2 Interrupt Sources and Configuration
sources (see Table 19-1). The vector codes that store the program start address when branching due to the generation of
a reset or various interrupt requests are two bytes each, so interrupts jump to a 64 K address of 00000H to 0FFFFH.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Maskable
Interrupt
The interrupt sources consist of maskable interrupts and software interrupts. In addition, they also have up to five reset
Type
Notes 1.
4.
2.
3.
Internal
External
Internal
Internal/
External
The default priority determines the sequence of interrupts if two or more maskable interrupts occur
simultaneously. Zero indicates the highest priority and 45 indicates the lowest priority.
Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 19-1.
When bit 7 (WDTINT) of the option byte (000C0H) is set to 1.
When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
Configuration
Basic
Type
Note 1
(A)
(B)
(A)
Priority
Default
10
11
12
13
14
15
16
17
18
19
20
0
1
2
3
4
5
6
7
8
9
Note 2
Table 19-1. Interrupt Source List (1/3)
INTWDTI
INTLVI
INTP0
INTP1
INTP2
INTP3
INTP4
INTP5
INTST3
INTSR3
INTSRE3
INTDMA0
INTDMA1
INTST0
INTCSI00
INTSR0
INTCSI01
INTSRE0
INTST1
INTCSI10
INTIIC10
INTSR1
INTSRE1
INTIICA
INTTM00
Name
Watchdog timer interval
(75% of overflow time)
Low-voltage detection
Pin input edge detection
End of UART3 transmission
End of UART3 reception
UART3 reception error occurrence
End of DMA0 transfer
End of DMA1 transfer
End of UART0 transmission
End of CSI00 communication
End of UART0 reception
End of CSI01 communication
CSI01/UART0 reception error occurrence
End of UART1 transmission
End of CSI10 communication
End of IIC10 communication
End of UART1 reception
UART1 reception error occurrence
End of IICA communication
End of timer channel 0 count or capture
Interrupt Source
Trigger
CHAPTER 19 INTERRUPT FUNCTIONS
Note 4
Note 3
Address
0000AH
0000CH
0000EH
0001AH
0001CH
0001EH
0002AH
0002CH
00004H
00006H
00008H
00010H
00012H
00014H
00016H
00018H
00020H
00022H
00024H
00026H
00028H
Vector
Table
LF
3
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
√
√
√
√
√
√
−
√
LG
3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
√
LH
3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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