UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 105

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Remark For extended SFRs (2nd SFRs), see Table 3-6 Extended SFR (2nd SFR) List.
Address
FFFD0H
FFFD1H
FFFD4H
FFFD5H
FFFD8H
FFFD9H
FFFDCH
FFFDDH
FFFE0H
FFFE1H
FFFE2H
FFFE3H
FFFE4H
FFFE5H
FFFE6H
FFFE7H
FFFE8H
FFFE9H
FFFEAH Priority specification flag register 01L
FFFEBH Priority specification flag register 01H
FFFECH Priority specification flag register 10L
FFFEDH Priority specification flag register 10H
FFFEEH Priority specification flag register 11L
FFFEFH Priority specification flag register 11H
FFFF0H
FFFF1H
FFFF2H
FFFF3H
FFFF4H
FFFF5H
FFFF6H
FFFF7H
Multiplication/division data register A (L)
Multiplication/division data register A (H)
Multiplication/division data register B (H)
Multiplication/division data register B (L)
Interrupt request flag register 2
Interrupt mask flag register 2
Priority specification flag register 02
Priority specification flag register 12
Interrupt request flag register 0L
Interrupt request flag register 0H
Interrupt request flag register 1L
Interrupt request flag register 1H
Interrupt mask flag register 0L
Interrupt mask flag register 0H
Interrupt mask flag register 1L
Interrupt mask flag register 1H
Priority specification flag register 00L
Priority specification flag register 00H
Special Function Register (SFR) Name
Table 3-5. SFR List (5/5)
MDAL/MULA
IF2L
IF2H
MK2L
MK2H
PR02L
PR02H
PR12L
PR12H
IF0L
IF0H
IF1L
IF1H
MK0L
MK0H
MK1L
MK1H
PR00L
PR00H
PR01L
PR01H
PR10L
PR10H
PR11L
PR11H
MDAH/MULB
MDBH/MULOH
MDBL/MULOL
Symbol
PR02
PR12
IF2
MK2
IF0
IF1
MK0
MK1
PR00
PR01
PR10
PR11
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Manipulable Bit Range
1-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
CHAPTER 3 CPU ARCHITECTURE
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
−
16-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
FFFFH
FFFFH
FFFFH
0000H
0000H
0000H
0000H
0000H
Reset
After
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
FFH
00H
00H
00H
00H
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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