UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 104

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Notes 1. The reset value of RESF varies depending on the reset source.
Address
FFF9DH Real-time counter control register 0
FFF9EH
FFF9FH
FFFA0H
FFFA1H
FFFA2H
FFFA3H
FFFA4H
FFFA5H
FFFA6H
FFFA8H
FFFA9H
FFFAAH Low-voltage detection level select register
FFFABH Watchdog timer enable register
FFFB0H
FFFB1H
FFFB2H
FFFB3H
FFFB4H
FFFB5H
FFFB6H
FFFB7H
FFFB8H
FFFB9H
FFFBAH DMA mode control register 0
FFFBBH DMA mode control register 1
FFFBCH DMA operation control register 0
FFFBDH DMA operation control register 1
FFFBEH Back ground event control register
FFFC0H
FFFC2H
FFFC4H
4. The reset value of WDTE is determined by the setting of the option byte.
5. Do not directly operate this SFR, because it is to be used in the self programming library.
2. The reset value of LVIM varies depending on the reset source and the setting of the option byte.
3. The reset value of LVIS varies depending on the reset source.
Real-time counter control register 1
Real-time counter control register 2
Clock operation mode control register
Clock operation status control register
Oscillation stabilization time counter status
register
Oscillation stabilization time select register
Clock control register
Clock output select register 0
Clock output select register 1
Reset control flag register
Low-voltage detection register
DMA SFR address register 0
DMA SFR address register 1
DMA RAM address register 0L
DMA RAM address register 0H
DMA RAM address register 1L
DMA RAM address register 1H
DMA byte count register 0L
DMA byte count register 0H
DMA byte count register 1L
DMA byte count register 1H
Special Function Register (SFR) Name
−
−
−
Table 3-5. SFR List (4/5)
RTCC0
RTCC1
RTCC2
CMC
CSC
OSTC
OSTS
CKC
CKS0
CKS1
RESF
LVIM
LVIS
WDTE
DSA0
DSA1
DRA0L
DRA0H
DRA1L
DRA1H
DBC0L
DBC0H
DBC1L
DBC1H
DMC0
DMC1
DRC0
DRC1
BECTL
PFCMD
PFS
FLPMC
Note 5
Symbol
Note 5
Note 5
DRA0
DRA1
DBC0
DBC1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
−
−
−
1-bit
√
√
√
−
√
√
−
√
√
√
−
√
√
−
−
−
−
−
−
−
−
−
−
−
√
√
√
√
√
−
−
−
Manipulable Bit
CHAPTER 3 CPU ARCHITECTURE
Range
8-bit
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
−
−
−
16-bit
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
−
√
√
√
√
−
−
−
−
−
−
−
−
After Reset
Undefined
Undefined
Undefined
Undefined
1A/9A
0EH
00H
C0H
00H
00H
00H
00H
00H
07H
09H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
00H
Note 1
Note 2
Note 3
Note 4
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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