UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 741

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
18.5.7 Forced termination by software
To forcibly terminate a DMA transfer by software without waiting for occurrence of the interrupt (INTDMAn) of DMAn,
therefore, perform either of the following processes.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
After DSTn is set to 0 by software, it takes up to 2 clocks until a DMA transfer is actually stopped and DSTn is set to 0.
<When using one DMA channel>
• Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software, confirm by polling
• Set the DSTn bit to 0 (use DRCn = 80H to write with an 8-bit manipulation instruction) by software and then set the
<When using both DMA channels>
• To forcibly terminate DMA transfer by software when using both DMA channels (by setting DSTn to 0), clear the
Remarks 1. n: DMA channel number (n = 0, 1)
that the DSTn bit has actually been cleared to 0, and then set the DENn bit to 0 (use DRCn = 00H to write with an 8-
bit manipulation instruction).
DENn bit to 0 (use DRCn = 00H to write with an 8-bit manipulation instruction) two or more clocks after.
DSTn bit to 0 after the DMA transfer is held pending by setting the DWAIT0 and DWAIT1 bits of both channels to 1.
Next, clear the DWAIT0 and DWAIT1 bits of both channels to 0 to cancel the pending status, and then clear the
DENn bit to 0.
2. 1 clock: 1/f
Example 1
DSTn = 0 ?
DENn = 0
DSTn = 0
Yes
CLK
Figure 18-13. Forced Termination of DMA Transfer (1/2)
(f
CLK
: CPU clock)
No
Example 2
2 clock wait
DENn = 0
DSTn = 0
CHAPTER 18 DMA CONTROLLER
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