UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 428

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
11.4 Operation of D/A Converter
11.4.1 Operation in normal mode
described below.
11.4.2 Operation in real-time output mode
as triggers.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
D/A conversion is performed using write operation to the DACSn register as the trigger. The setting method is
<1> Set bit 6 (DACEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the D/A
<2> Set the DAMDn bit of the D/A converter mode register (DAM) to 0 (normal mode).
<3> Use the bit 6 (DAREF) of the DAM register to select the D/A converter reference voltage supply on the positive
<4> Use the DARESn bit of the DAM register to select the resolution of the D/A converter.
<5> Set the analog voltage value to be output to the ANOn pin to the D/A conversion value setting register Wn
<6> Set the DACEn bit of the DAM register to 1 (D/A conversion enable).
<7> To perform subsequent D/A conversions, write to the DACSWn or DACSn register.
Cautions 1. Even if 1, 0, and then 1 is set to the DACEn bit, there is a wait after 1 is set for the last time.
Remark n = 0, 1
D/A conversion is performed using the interrupt request signals (INTTM04 and INTTM05)
The setting method is described below.
Note Channel 0 of the D/A converter: INTTM04
<1> Set bit 6 (DACEN) of peripheral enable register 0 (PER0) to 1 to start the supply of the input clock to the D/A
<2> Set the DAMDn bit of the D/A converter mode register (DAM) to 0 (normal mode).
<3> Use the bit 6 (DAREF) of the DAM register to select the D/A converter reference voltage supply on the positive
<4> Use the DARESn bit of the DAM register to select the resolution of the D/A converter.
<5> Set the analog voltage value to be output to the ANOn pin to the D/A conversion value setting register Wn
side.
(DACSWn) or D/A conversion value setting register n (DACSn).
Steps <1> and <5> above constitute the initial settings.
After the wait time (20
elapses, the D/A converted analog voltage value is output from the ANOn pin.
The previous D/A conversion result is held until the next D/A conversion is performed.
When the DACEn bit of the DAM register is set to 0 (D/A conversion operation stop), D/A conversion stops, the
ANOn pin goes into a high-impedance state when the PM11n bit of the PM11 register = 1 (input mode), and the
ANOn pin outputs the set value of the P11 register when the PM11n bit = 0 (output mode).
side.
(DACSWn) or D/A conversion value setting register n (DACSn).
converter.
converter.
Channel 1 of the D/A converter: INTTM05
2. If the DACSWn or DACSn register is rewritten during the settling time, D/A conversion is aborted
and reconversion by using the rewritten values starts.
μ
s or more) elapses, D/A conversion starts, and then, after the settling time (18
CHAPTER 11 D/A CONVERTER
Note
of timer channels 4 and 5
μ
s (max.))
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