UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 440
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 440 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
13.3 Amplifier Registers Used in Voltage Reference
(1) Peripheral enable register 0 (PER0)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(2) Analog reference voltage control register (ADVRC)
The voltage reference uses the following two registers.
• Peripheral enable register 0 (PER0)
• Analog reference voltage control register (ADVRC)
PER0 is used to enable or disable use of each peripheral hardware macro. Clock supply to a hardware macro that is
not used is stopped in order to reduce the power consumption and noise.
When the voltage reference is used, be sure to set bit 5 (ADCEN) of this register to 1.
PER0 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
This register is used to select the reference voltage supplies of the A/D and D/A converters, control the operation of
the input gate voltage boost circuit for the A/D converter, and control the voltage reference (VR) operation.
ADVRC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: F00F0H
Symbol
PER0
Note
Caution When setting voltage reference, be sure to set ADCEN to 1 first. If ADCEN = 0, writing to
ADCEN
RTCEN
<7>
78K0R/LG3, 78K0R/LH3 only
0
1
After reset: 00H
a control register of voltage reference is ignored, and, even if the register is read, only
the default value is read.
Figure 13-2. Format of Peripheral Enable Register 0 (PER0)
Stops input clock supply.
• SFR used by the A/D converter, operational amplifier, and voltage reference cannot be
• The A/D converter, operational amplifier, and voltage reference is in the reset status.
Supplies input clock.
• SFR used by the A/D converter, operational amplifier, and voltage reference can be read
DACEN
written.
and written.
<6>
Control of A/D converter, operational amplifier, and voltage reference input clock
R/W
ADCEN
<5>
IICAEN
<4>
Note
SAU1EN
<3>
CHAPTER 13 VOLTAGE REFERENCE
SAU0EN
<2>
TAU1EN
<1>
TAU0EN
<0>
440
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