UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 283
UPD78F1506GF-GAT-AX
Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet
1.UPD78F1500GK-GAK-AX.pdf
(1016 pages)
Specifications of UPD78F1506GF-GAT-AX
Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- Current page: 283 of 1016
- Download datasheet (7Mb)
78K0R/Lx3
• 78K0R/LF3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F01B4H, F01B5H
Address: F01DCH, F01DDH
Address: FFF3EH
Address: FFF3EH
(8) Timer input select registers 0, 1 (TIS0, TIS1)
Symbol
Symbol
Symbol
Symbol
TIS0
TIS1
TT0
TT1
Caution Be sure to clear bits 15 to 8 of TT0 and bits 15 to 4 of TT1 to “0”.
Remarks 1. When the TTm register is read, 0 is always read.
TIS0 and TIS1 use can be set to the input signal of a timer input pin (TIpq), half the frequency of the subsystem
clock (f
the timer input. The timer input can be selected for each channel.
TIS0 and TIS1 can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Remark
TTmn
SUB
15
15
0
1
0
0
TIS07
2. mn: Unit number + Channel number
/2), one fourth the frequency of the subsystem clock (f
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
7
7
0
After reset: 00H
After reset: 00H
No trigger operation
Operation is stopped (stop trigger is generated).
m = 0, 1, mn = 00 to 07, 10 to 13
14
14
0
0
Figure 6-17. Format of Timer Input Select Registers 0, 1 (TIS0, TIS1) (1/2)
After reset: 0000H
13
13
Figure 6-16. Format of Timer Channel Stop Register m (TTm)
After reset: 0000H
0
0
6
0
6
0
12
12
0
0
R/W
R/W
11
11
RTCIS04
0
0
5
0
5
R/W
10
R/W
10
0
0
Operation stop trigger of channel n
RTCIS00
9
0
9
0
TIS04
4
4
8
0
8
0
TT07 TT06 TT05 TT04 TT03 TT02 TT01 TT00
7
7
0
TIS03
3
3
0
SUB
6
6
0
/4), or an RTC interval interrupt (INTRTCI) as
CHAPTER 6 TIMER ARRAY UNIT
5
5
0
TIS02
2
2
0
4
4
0
TT13 TT12 TT11 TT10
3
3
TIS01
1
1
0
2
2
1
1
TIS00
0
0
0
0
0
283
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