UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 993

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Low-
voltage
detector
Function
Used as reset
(when detecting
level of supply
voltage (V
(LVIOFF = 1)
Used as reset
(when detecting
level of supply
voltage (V
(LVIOFF = 0)
Used as reset
(when detecting
level of input
voltage from
external input
pin (EXLVI))
Used as
interrupt (when
detecting level of
supply voltage
(V
0)
Used as
interrupt (when
detecting level of
input voltage
from external
input pin
(EXLVI))
DD
Details of
Function
)) (LVIOFF =
DD
DD
))
))
Be sure to execute <1>. When LVIMK = 0, an interrupt may occur immediately after
the processing in <4>.
If supply voltage (V
reset signal is not generated.
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
Be sure to execute <1>. When LVIMK = 0, an interrupt may occur immediately after
the processing in <3>.
If input voltage from external input pin (EXLVI) ≥ detection voltage (V
(TYP.)) when LVIMD is set to 1, an internal reset signal is not generated.
Input voltage from external input pin (EXLVI) must be EXLVI < V
Even when the LVI default start function is used, if it is set to LVI operation
prohibition by the software, it operates as follows:
• Does not perform low-voltage detection during LVION = 0.
• If a reset is generated while LVION = 0, LVION will be re-set to 1 when the CPU
When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, the
LVIRF flag may become 1 from the beginning due to the power-on waveform.
For details of RESF, see CHAPTER 22 RESET FUNCTION.
Input voltage from the external input pin (EXLVI) must be EXLVI < V
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
starts after reset release. There is a period when low-voltage detection cannot be
performed normally, however, when a reset occurs due to WDT and illegal
instruction execution.
This is due to the fact that while the pulse width detected by LVI must be 200
max., LVION = 1 is set upon reset occurrence, and the CPU starts operating
without waiting for the LVI stabilization time.
DD
) ≥ detection voltage (V
Cautions
LVI
) when LVIMD is set to 1, an internal
APPENDIX C LIST OF CAUTIONS
DD
.
DD
.
EXLVI
= 1.21 V
μ
μ
s
s
p.816
p.816
p.818
p.820
p.820
p.820
p.824
p.824
p.826
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