UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 727

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: FFFBAH (DMC0), FFFBBH (DMC1)
Symbol
DMCn
Note The software trigger (STGn) can be used regardless of the IFCn0 to IFCn3 values.
Remarks 1. n: DMA channel number (n = 0, 1)
IFCn
3
0
0
0
0
0
0
0
1
1
1
1
1
STGn
<7>
Other than above
2. √: Supported, −: Not supported
IFCn
2
0
0
0
1
1
1
1
0
0
0
0
1
Figure 18-4. Format of DMA Mode Control Register n (DMCn) (2/2)
IFCn
1
0
1
1
0
0
1
1
0
0
1
1
0
DRSn
<6>
IFCn
0
0
0
1
0
1
0
1
0
1
0
1
0
INTTM00
INTTM01
INTTM04
INTTM05
INTST0
INTCSI00
INTSR0
INTCSI01
INTST1
INTCSI10
INTIIC10
INTSR1
INTST3
INTSR3
INTAD
Trigger signal
After reset: 00H
DSn
<5>
−
Selection of DMA start source
DWAITn
Disables DMA transfer by interrupt.
(Only software trigger is enabled.)
Timer channel 0 interrupt
Timer channel 1 interrupt
Timer channel 4 interrupt
Timer channel 5 interrupt
UART0 transmission end interrupt
CSI00 transfer end interrupt
UART0 reception end interrupt
CSI01 transfer end interrupt
UART1 transmission end interrupt
CSI10 transfer end interrupt
IIC10 transfer end interrupt
UART1 reception end interrupt
UART3 transmission end interrupt
UART3 reception end interrupt
A/D conversion end interrupt
<4>
R/W
Trigger contents
IFCn3
Setting prohibited
3
Note
CHAPTER 18 DMA CONTROLLER
IFCn2
2
LF3
IFCn1
√
√
√
√
√
−
−
−
−
√
√
√
√
√
√
√
1
LG3
√
√
√
√
√
√
√
√
−
√
√
√
√
√
√
√
IFCn0
0
LH3
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
√
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