UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 215

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

X2/EXCLK
Option byte(000C1H)
FRQSEL2,
FRQSEL1
XT2//P124
XT1/P123
X1/P121
Clock operation mode
/P122
AMPHS1
control register
AMPHS0
(CMC)
AMPH
Crystal/ceramic
oscillation (8 MHz (typ.))
oscillation (20 MHz (typ.))
External input
oscillation (1 MHz (typ.))
Internal high-speed
Internal high-speed
I
nternal high-speed
high-speed oscillator
High-speed system
oscillation
Internal high-speed
oscillation
Subsystem clock
20 MHz internal
Clock operation mode
control register
(CMC)
Crystal
EXCLK OSCSEL
clock
clock oscillator
OSCSELS
oscillator
oscillator
f
f
f
f
IH20
f
f
EX
IH1
XT
X
IH8
Clock operation status
f
f
f
f
MX
SUB
IH
IH20
control register
Clock operation status
oscillation (30 kHz (typ.))
(CSC)
Internal low-speed
Internal low-speed
CLS
control register
oscillator
MSTOP
(CSC)
XTSTOP HIOSTOP
STOP mode
signal
f
IL
<R>
DSCS
MOST
8
SELDSC
Figure 5-1. Block Diagram of Clock Generator
Option byte(000C0H)
WDTON
WDSTBYON
MOST
HALT/STOP mode signal
9
stabilization time counter
OSTS2
MOST
20 MHz internal high-speed
oscillation control register
(DSCCTL)
10
DSCON
X1 oscillation
MOST
OSTS1 OSTS0
11
Internal bus
MOST
3
Watchdog timer
13
Oscillation stabilization time
counterstatus register
(OSTC)
Oscillation stabilization
time select register (OSTS)
MOST
Internal bus
15
MOST
17
MOST
18
Main system
clock source
selection
f
MAIN
CLS
Clock output/
buzzer output
CSS
f
f
f
f
f
f
f
f
MAIN
MAIN
MAIN
MAIN
MAIN
MAIN
SUB
SUB
Real-time counter,
clock output/buzzer output
/2
/2
/2
/2
/2
/2
MCS
5
4
3
2
SDIV
MCM0
f
f
MAINC
SUBC
RTC
SDIV
EN
System clock control
register (CKC)
MD
IV2
DAC
EN
CPU clock and
hardware clock
Selection of
peripheral
source
MD
IV1
ADC
f
3
SUBC
EN
MD
IV0
/2
f
IICA
CLK
EN
Timer array unit 0
SAU1
EN
Peripheral enable register 0
(PER0)
Standby control circuit
(see CHAPTER 24)
Normal operation
SAU0
STOP mode
HALT mode
EN
mode
TAU1
EN
CPU
TAU0
EN
Timer array unit 0
Timer array unit 1
Serial array unit 0
Serial array unit 1
Serial interface IICA
A/D converter, operational Amplifiers, voltage reference
D/A converter
Real-time counter