UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 715

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(1) Multiplication/division data register A (MDAH, MDAL)
Symbol
Symbol
The MDAH and MDAL registers set the values that are used for a multiplication or division operation and store the
operation result. They set the multiplier and multiplicand data in the multiplication mode, and set the dividend data
in the division mode. Furthermore, the operation result (quotient) is stored in the MDAH and MDAL registers in the
division mode.
MDAH and MDAL can be set by a 16-bit manipulation instruction.
Reset signal generation clears these registers to 0000H.
Cautions 1. Do not rewrite the MDAH and MDAL values during division operation processing (while the
The following table shows the functions of MDAH and MDAL during operation execution.
Remark
Address:
MDAH
MDAL
DIVMODE
0
1
FFFF0H, FFFF1H, FFFF2H, FFFF3H
MDAH
MDAL
DIVMODE: Bit 7 of the multiplication/division control register (MDUC)
2. The MDAH and MDAL values read during division operation processing (while MDUC is 81H)
15
15
Figure 17-2. Format of Multiplication/Division Data Register A (MDAH, MDAL)
multiplication/division control register (MDUC) is 81H). The operation will be executed in this
case, but the operation result will be an undefined value.
will not be guaranteed.
MDAH
MDAL
Table 17-2. Functions of MDAH and MDAL During Operation Execution
14
14
Multiplication mode
Division mode
MDAH
MDAL
Operation Mode
13
13
MDAH
MDAL
12
12
FFFF3H
FFFF1H
MDAH
MDAL
11
11
MDAH
MDAL
10
10
After reset: 0000H, 0000H R/W
MDAH: Multiplier
MDAL: Multiplicand
MDAH: Divisor (higher 16 bits)
MDAL: Dividend (lower 16 bits)
MDAH
MDAL
9
9
MDAH
MDAL
8
8
Setting
MDAH
MDAL
7
7
MDAH
MDAL
6
6
CHAPTER 17 MULTIPLIER/DIVIDER
MDAH
MDAL
5
5
MDAH: Division result (quotient)
MDAL: Division result (quotient)
MDAH
MDAL
FFFF2H
4
FFFF0H
4
Higher 16 bits
Lower 16 bits
MDAH
MDAL
Operation Result
3
3
MDAH
MDAL
−
2
2
MDAH
MDAL
1
1
MDAH
MDAL
0
0
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