UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 545

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
14.6.3 LIN transmission
Note Use this operation within a range that satisfies the conditions above and the AC characteristics in the electrical
Remarks 1. f
reduce the cost of an automobile network.
this frame and corrects a baud rate error from the master. If the baud rate error of a slave is within ±15%, communication
can be established.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Of UART transmission, UART3 supports LIN communication.
For LIN transmission, channel 2 of unit 1 (SAU1) is used.
LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol designed to
Communication of LIN is single-master communication and up to 15 slaves can be connected to one master.
The slaves are used to control switches, actuators, and sensors, which are connected to the master via LIN.
Usually, the master is connected to a network such as CAN (Controller Area Network).
A LIN bus is a single-wire bus to which nodes are connected via transceiver conforming to ISO9141.
According to the protocol of LIN, the master transmits a frame by attaching baud rate information to it. A slave receives
Figure 14-82 outlines a transmission operation of LIN.
Support of LIN communication
Target channel
Pins used
Interrupt
Error detection flag
Transfer data length
Transfer rate
Data phase
Parity bit
Stop bit
Data direction
specifications (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
2. For 78K0R/LF3, UART0 is not mounted.
f
MCK
CLK
UART
: System clock frequency
: Operation clock (MCK) frequency of target channel
Not supported
Transfer end interrupt (in single-transfer mode) or buffer empty interrupt (in continuous transfer
mode) can be selected.
None
8 bits
Max. f
Forward output (default: high level)
Reverse output (default: low level)
The following selectable
• No parity bit
• Appending 0 parity
• Appending even parity
• Appending odd parity
The following selectable
• Appending 1 bit
• Appending 2 bits
MSB or LSB first
MCK
UART0
/6 [bps] (SDRmn [15:9] = 2 or more), Min. f
−
−
−
Not supported
UART1
−
−
−
Not supported
CHAPTER 14 SERIAL ARRAY UNIT
CLK
/(2 × 2
UART2
−
−
−
11
× 128) [bps]
Supported
Channel 2 of SAU1
TxD3
INTST3
Note
UART3
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