UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 223

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
78K0R/Lx3
(5) System clock control register (CKC)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
This register is used to select a CPU/peripheral hardware clock and a division ratio.
CKC can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 09H.
Address: FFFA4H
Symbol
CKC
Notes 1. Bits 7 and 5 are read-only.
(Remarks and Cautions are listed on the next page.)
MCS
1
CLS
CLS
CSS
<7>
Note 4
2. Setting is prohibited when f
3. Setting is prohibited when f
4. Changing the value of the MCM0 bit is prohibited while CSS is set to 1.
0
1
0
1
0
0
After reset: 09H
Figure 5-6. Format of System Clock Control Register (CKC)
Main system clock (f
Subsystem clock (f
Internal high-speed oscillation clock (f
(f
High-speed system clock (f
IH20
MCM0
×
CSS
<6>
)
Note 4
0
1
R/W
SDIV
MCS
Other than above
<5>
Note 1
×
×
×
×
×
×
×
×
×
×
×
×
0
1
SUB
MAIN
)
Status of CPU/peripheral hardware clock (f
)
IH
MX
MX
= 1 MHz.
< 4 MHz.
Status of Main system clock (f
)
MDIV2
MCM0
<4>
0
0
0
0
1
1
0
0
0
0
1
1
×
×
IH
) or 20 MHz internal high-speed oscillation clock
MDIV1
SDIV
0
0
1
1
0
0
0
0
1
1
0
0
×
×
3
CHAPTER 5 CLOCK GENERATOR
MDIV0
MDIV2
0
1
0
1
0
1
0
1
0
1
0
1
×
×
MAIN
2
)
CLK
f
f
f
f
f
f
f
f
f
f
f
f
f
f
Setting prohibited
IH
IH
IH
IH
IH
IH
MX
MX
MX
MX
MX
MX
SUB
SUB
)
/2 (default)
/2
/2
/2
/2
hardware clock (f
MDIV1
/2
/2
/2
/2
/2
/2
2
3
4 Note 2
5 Note 2
2
3
4
5 Note 3
CPU/peripheral
1
Selection of
MDIV0
0
CLK
)
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