UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 275

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F01A0H, F01A1H (TSR00) to F01AEH, F01AFH (TSR07)
(4) Timer status register pq (TSRpq)
Symbol
TSRpq
TSRpq indicates the overflow status of the counter of channel n.
TSRpq is valid only in the capture mode (MDpq3 to MDpq1 = 010B) and capture & one-count mode (MDpq3 to
MDpq1 = 110B). It will not be set in any other mode. See Table 6-3 for the operation of the OVFpq bit in each
operation mode and set/clear conditions.
TSRpq can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of TSRpq can be set with an 8-bit memory manipulation instruction with TSRpqL.
Reset signal generation clears this register to 0000H.
Remark
Remark The OVFpq bit does not change immediately after the counter has overflowed, but changes upon the
F01D0H, F01D1H (TSR10) to F01D6H, F01D7H (TSR13)
When OVFpq = 1, this flag is cleared (OVFpq = 0) when the next value is captured without overflow.
• Capture mode
• Capture & one-count mode
• Interval timer mode
• Event counter mode
• One-count mode
OVF
15
pq
0
0
1
Table 6-3. OVFpq Bit Operation and Set/Clear Conditions in Each Operation Mode
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
78K0R/LF3: pq = 00 to 04, 07
78K0R/LG3: pq = 00 to 07
78K0R/LH3: pq = 00 to 07, 10 to 13
subsequent capture.
Timer operation mode
Overflow does not occur.
Overflow occurs.
14
0
13
0
Figure 6-8. Format of Timer Status Register pq (TSRpq)
12
0
11
0
clear
set
clear
set
OVFpq
10
0
Counter overflow status of channel q
When no overflow has occurred upon capturing
When an overflow has occurred upon capturing
9
0
8
0
After reset: 0000H
7
0
(Use prohibited, not set/cleared)
6
0
Set/clear conditions
CHAPTER 6 TIMER ARRAY UNIT
5
0
R
−
4
0
3
0
2
0
1
0
OVF
pq
0
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