UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 320

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
TAU
default
setting
Channel
default
setting
Operation
start
During
operation
Operation
stop
Remark
Sets the TAU0EN or TAU1EN bits of the PER0 register
to 1.
Sets the TPSp register.
Sets the TMRpq register (determines operation mode of
channel).
Sets interval (period) value to the TDRpq register.
Clears the TOMpq bit of the TOMp register to 0 (toggle
mode).
Clears the TOLpq bit to 0.
Sets the TOpq bit and determines default level of the
TOpq output.
Sets TOEpq to 1 and enables operation of TOpq.
Clears the port register and port mode register to 0.
Sets the TOEpq to 1 (only when operation is resumed).
Sets the TSpq bit to 1.
Set value of the TDRpq register can be changed.
The TCRpq register can always be read.
The TSRpq register is not used.
Set values of TOp and TOEp registers can be changed.
Set values of TMRpq, TOMp, and TOLp registers cannot
be changed.
The TTpq bit is set to 1.
TOEpq is cleared to 0 and value is set to the TOp
register.
pq: Unit number + Channel number (only for channels provided with timer I/O pins)
pq = 00, 02 to 04
Determines clock frequencies of CKp0 and CKp1.
The TSpq bit automatically returns to 0 because it is a
trigger bit.
The TTpq bit automatically returns to 0 because it is a
trigger bit.
Figure 6-48. Operation Procedure When Frequency Divider Function Is Used (1/2)
Software Operation
Power-off status
Power-on status. Each channel stops operating.
Channel stops operating.
(Clock is supplied and some power is consumed.)
The TOpq pin goes into Hi-Z output state.
The TOpq default setting level is output when the port mode
register is in output mode and the port register is 0.
TOpq does not change because channel stops operating.
The TOpq pin outputs the TOpq set level.
TEpq = 1, and count operation starts.
Counter (TCRpq) counts down. When count value reaches
0000H, the value of TDRpq is loaded to TCRpq again, and
the count operation is continued. By detecting TCRpq =
0000H, INTTMpq is generated and TOpq performs toggle
operation.
After that, the above operation is repeated.
TEpq = 0, and count operation stops.
The TOpq pin outputs the TOpq set level.
(Clock supply is stopped and writing to each register is
disabled.)
(Clock supply is started and writing to each register is
enabled.)
Value of TDRpq is loaded to TCRpq at the count clock
input. INTTMpq is generated and TOpq performs toggle
operation if the MDpq0 bit of the TMRpq register is 1.
TCRpq holds count value and stops.
The TOpq output is not initialized but holds current status.
CHAPTER 6 TIMER ARRAY UNIT
Hardware Status
320