UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 802

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
22.1 Register for Confirming Reset Source
is used to store which source has generated the reset request.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Many internal reset generation sources exist in the 78K0R/Lx3 microcontrollers. The reset control flag register (RESF)
RESF can be read by an 8-bit memory manipulation instruction.
RESET input, reset by power-on-clear (POC) circuit, and reading RESF clear TRAP, WDRF, and LVIRF.
Notes 1.
Cautions 1. Do not read data by a 1-bit memory manipulation instruction.
The status of RESF when a reset request is generated is shown in Table 22-3.
Address: FFFA8H
Flag
TRAP
WDRF
LVIRF
Symbol
RESF
2.
2. Do not make a judgment based on only the read value of the RESF register 8-bit data, because
3. When the LVI default start function (bit 0 (LVIOFF) of 000C1H = 0) is used, LVIRF flag may
The value after reset varies depending on the reset source.
The illegal instruction is generated when instruction code FFH is executed.
Reset by the illegal instruction execution not issued by emulation with the in-circuit emulator or on-chip
debug emulator.
bits other than TRAP, WDRF, and LVIRF become undefined.
become 1 from the beginning depending on the power-on waveform.
Reset Source
TRAP
WDRF
LVIRF
TRAP
7
0
1
0
1
0
1
Note 1
After reset: Undefined
Table 22-3. RESF Status When Reset Request Is Generated
Figure 22-5. Format of Reset Control Flag Register (RESF)
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Internal reset request is not generated, or RESF is cleared.
Internal reset request is generated.
Undefined
Cleared (0)
RESET Input
6
Undefined
Internal reset request by execution of illegal instruction
Cleared (0)
Reset by POC
5
R
Internal reset request by low-voltage detector (LVI)
Internal reset request by watchdog timer (WDT)
WDRF
4
Note 1
Set (1)
Held
Held
Reset by Execution
of Illegal Instruction
Undefined
3
Undefined
CHAPTER 22 RESET FUNCTION
2
Held
Set (1)
Held
Reset by WDT
Undefined
Note 2
1
Held
Held
Set (1)
Reset by LVI
LVIRF
0
Note 1
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