UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 461

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Address: F0100H, F0101H (SSR00) to F0106H, F0107H (SSR03),
SSRmn
Symbol
Note Only SSR12 register does not have FET12, PET12, and OVF12.
Remark
F0140H, F0141H (SSR10), F0142H, F0143H (SSR11),
F0144H, F0145H (SSR12), F0146H, F0147H (SSR13)
This is a cumulative flag and is not cleared until 1 is written to the FECTmn bit of the SIRmn register.
This is a cumulative flag and is not cleared until 1 is written to the PECTmn bit of the SIRmn register.
This is a cumulative flag and is not cleared until 1 is written to the OVCTmn bit of the SIRmn register.
OVF
FEF
PEF
mn
mn
mn
15
0
1
0
1
0
1
0
m: Unit number (m = 0, 1), n: Channel number (n = 0 to 3)
No error occurs.
A framing error occurs during UART reception.
Error does not occur.
A parity error occurs during UART reception or ACK is not detected during I
No error occurs.
An overrun error occurs.
14
0
<Framing error cause>
A framing error occurs if the stop bit is not detected upon completion of UART reception.
<Parity error cause>
• A parity error occurs if the parity of transmit data does not match the parity bit on completion of UART
• ACK is not detected if the ACK signal is not returned from the slave in the timing of ACK reception
<Causes of overrun error>
• Receive data stored in the SDRmn register is not read and transmit data is written or the next receive
• Transmit data is not ready for slave transmission or reception in the CSI mode.
reception.
during I
data is written.
Figure 14-9. Format of Serial Status Register mn (SSRmn) (2/2)
13
0
2
C transmission.
12
0
11
0
10
0
Framing error detection flag of channel n
Overrun error detection flag of channel n
Parity error detection flag of channel n
9
0
8
0
After reset: 0000H
7
0
TSF
mn
6
CHAPTER 14 SERIAL ARRAY UNIT
BFF
mn
5
R
2
4
0
C transmission.
3
0
FEF
mn
Note
2
PEF
mn
Note
1
OVF
mn
Note
0
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