UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 59

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
2.2.8 P70 to P77
I/O.
port input mode register 7 (PIM7).
output mode register 7 (POM7).
(1) Port mode
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(2) Control mode
P70 to P77 function as an I/O port. This port can also be used for key return input, serial interface clock I/O, and data
Input to the P75, and P76 pins can be specified through a normal input buffer or a TTL input buffer in 1-bit units using
Output from the P75, and P77 pins can be specified as N-ch open-drain output (V
The following operation modes can be specified in 1-bit units.
Caution To use P75/SCK01/KR5, P76/SI01/KR6, and P77/SO01/KR7, as a general-purpose port, note the serial
P70/KR0
P71/KR1
P72/KR2
P73/KR3
P74/KR4
P75/SCK01
P76/KR6/SI01
P77/KR7/SO01
P70 to P77 function as an I/O port. P70 to P77 can be set to input or output port in 1-bit units using port mode
register 7 (PM7). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 7 (PU7).
P70 to P77 function as key interrupt input, serial interface clock I/O, and data I/O.
(a) KR0 to KR7
(b) SCK01
(c) SI01
(d) SO01
These are the key return input pins
This is a clock I/O pin of serial interface CSI01.
This is a serial data input pin of serial interface CSI01.
This is a serial data output pin of serial interface CSI01.
array unit 0 setting. For details, refer to Table 14-6 Relationship Between Register Settings and Pins
(Channel 1 of unit 0: CSI01, UART0 Reception).
(80 pins:
78F1501A, 78F1502A)
78K0R/LF3
μ
PD78F1500A,
−
−
−
−
−
−
−
−
(100 pins:
78F1504A, 78F1505A)
78K0R/LG3
μ
PD78F1503A,
CHAPTER 2 PIN FUNCTIONS
DD
tolerance) in 1-bit units using port
(128 pins:
78F1507A, 78F1508A)
78K0R/LH3
μ
PD78F1506A,
√
√
√
√
√
√
√
√
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