UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 971

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Timer
array unit
Function
TMRmn: Timer
mode register
mn
TSm: Timer
channel start
register m
Start Timing (In
Interval Timer
Mode)
Start Timing (In
Capture Mode)
Start Timing (In
One-count Mode
and In Capture &
One-count
Mode)
TTm: Timer
channel stop
register m
TISp: Timer
input select
register p
TOEp: Timer
output enable
register p
TOp: Timer
output register p
TOLp: Timer
output level
register p
TOMp: Timer
output mode
register p
Details of
Function
Be sure to clear bits 14, 13, 5, and 4 to “0”.
Channel 5 of timer array unit 0 and channels 0 to 3 of timer array unit 1 of the
78K0R/LF3 can be set only to the interval mode.
Channel 6 of timer array unit 0 of the 78K0R/LF3 can be set only to the interval mode
and one-count mode (when using as master).
Channels 0 to 3 of timer array unit 1 of the 78K0R/LG3 can be set only to the interval
mode.
Be sure to clear bits 15 to 8 of TS0 and bits 15 to 4 of TS1 to “0”.
In the first cycle operation of count clock after writing TSmn, an error at a maximum
of one clock is generated since count start delays until count clock has been
generated. When the information on count start timing is necessary, an interrupt can
be generated at count start by setting MDmn0 = 1.
In the first cycle operation of count clock after writing TSpq, an error at a maximum of
one clock is generated since count start delays until count clock has been generated.
When the information on count start timing is necessary, an interrupt can be
generated at count start by setting MDpq0 = 1.
An input signal sampling error is generated since operation starts upon start trigger
detection (The error is one count clock when TIpq is used).
Be sure to clear bits 15 to 8 of TT0 and bits 15 to 4 of TT1 to “0”.
When the LIN-bus communication function is used, select the input signal of the
RxD3 pin by setting ISC1 to 1 and TIS07 = 0.
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOE0 to “0”.
For 78K0R/LG3, be sure to clear bits 15 to 8 of TOE0 to “0”.
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOE0, bits 15 to 4 of TOE1 to “0”.
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TO0 to “0”.
For 78K0R/LG3, be sure to clear bits 15 to 8 of TO0 to “0”.
For 78K0R/LH3, be sure to clear bit 15 to 8 of TO0, bits 15 to 4 of TO1 to “0”.
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOL0 to “0”.
For 78K0R/LG3, be sure to clear bits 15 to 8 of TOL0 to “0”.
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOL0, bits 15 to 4 of TOL1 to “0”.
For 78K0R/LF3, be sure to clear bits 15 to 8, 6 and 5 of TOM0 to “0”.
For 78K0R/LG3, be sure to clear bits 15 to 8 of TOM0 to “0”.
For 78K0R/LH3, be sure to clear bit 15 to 8 of TOM0, bits 15 to 4 of TOM1 to “0”.
Cautions
APPENDIX C LIST OF CAUTIONS
p.289
pp.271
to 273
pp.273,
278
pp.273,
278
pp.273,
278
p.277
p.279
p.280
pp.281,
282
p.283
p.284
p.286
p.286
p.286
p.287
p.287
p.287
p.288
p.288
p.288
p.289
p.289
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