UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 987

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
LCD
controller/d
river
Multiplier/d
ivider
DMA
controller
Function
ISC: Input switch
control register
Internal voltage
boosting method
Capacitor spli
method
External
resistance
division method
Selection of LCD
display data
MDAH, MDAL:
Multiplication/divi
sion data
register A
MDBL, MDBH:
Multiplication/divi
sion data
register B
MDCL, MDCH:
Multiplication/divi
sion data
register C
MDUC:
Multiplication/divi
sion control
register
DBCn: DMA
byte count
register n
DRCn: DMA
operation control
register n
Holding DMA
transfer pending
by DWAITn
Forced
termination of
DMA transfer
Details of
Function
t
Be sure to clear bits 5 to 7 to “0”.
When stopping the operation of the voltage boost circuit circuit, be sure to set SCOC
and LCDON to 0 before setting VLCON to 0.
When stopping the operation of the capacitor split circuit, be sure to set SCOC and
LCDON to 0 before setting VLCON to 0.
To stabilize the potential of the V
capacitor of about 0.1
as needed.
When the LCD display data memory is used when the number of time slices is eight,
LCD display data (A-pattern, B-pattern, or blinking display) cannot be selected.
Do not rewrite the MDAH and MDAL values during division operation processing
(while the multiplication/division control register (MDUC) is 81H). The operation will
be executed in this case, but the operation result will be an undefined value.
The MDAH and MDAL values read during division operation processing (while
MDUC is 81H) will not be guaranteed.
Do not rewrite the MDBH and MDBL values during division operation processing
(while the multiplication/division control register (MDUC) is 81H).
result will be an undefined value.
Do not set MDBH and MDBL to 0000H in the division mode. If they are set, the
operation result will be an undefined value.
The MDCH and MDCL values read during division operation processing (while the
multiplication/division control register (MDUC) is 81H) will not be guaranteed.
Do not rewrite DIVMODE during operation processing (while DIVST is 1). If it is
rewritten, the operation result will be an undefined value.
DIVST cannot be cleared (0) by using software during division operation processing
(while DIVST is 1).
Be sure to clear bits 15 to 10 to “0”.
If the general-purpose register is specified or the internal RAM space is exceeded as
a result of continuous transfer, the general-purpose register or SFR space are written
or read, resulting in loss of data in these spaces. Be sure to set the number of times
of transfer that is within the internal RAM space.
The DSTn flag is automatically cleared to 0 when a DMA transfer is completed.
Writing the DENn flag is enabled only when DSTn = 0. When a DMA transfer is
terminated without waiting for generation of the interrupt (INTDMAn) of DMAn,
therefore, set DSTn to 0 and then DENn to 0 (for details, refer to 18.5.7 Forced
termination by software).
When the FSEL bit of the OSMC register has been set to 1, do not enable (DENn =
1) DMA operation for at least three clocks after the setting.
When DMA transfer is held pending while using both DMA channels, be sure to held
the DMA transfer pending for both channels (by setting DWAIT0 and DWAIT1 to 1).
If the DMA transfer of one channel is executed while that of the other channel is held
pending, DMA transfer might not be held pending for the latter channel.
In example 3, the system is not required to wait two clock cycles after the DWAITn bit
is set to 1. In addition, the system does not have to wait two clock cycles after
clearing the DSTn bit to 0, because more than two clock cycles elapse from when the
DSTn bit is cleared to 0 to when the DENn bit is cleared to 0.
μ
F between each of the pins from V
LC0
Cautions
to V
LC3
pins, it is recommended to connect a
APPENDIX C LIST OF CAUTIONS
LC0
to V
LC3
and the GND pin
The operation
p.679
p.684
p.685
pp.708
,709
p.711
p.728
p.715
p.715
p.716
p.716
p.717
p.718
p.718
p.725
p.725
p.728
p.740
p.742
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