UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 413

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
(3) Timer trigger mode (Continuous conversion mode)
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
<1> Timer trigger mode is set and a timer trigger wait state is entered by setting bit 7 (ADTMD) of A/D converter mode
<2> When the timer trigger signal is detected, bit 7 (ADCS) of the A/D converter mode register (ADM) is automatically
<3> When A/D conversion has been completed, the result of the A/D conversion is stored in the A/D conversion result
<4> If 1 is written to ADS during A/D conversion, the A/D conversion operation under execution is stopped and
<5> If a timer trigger signal is generated during A/D conversion, the A/D conversion operation under execution is
<6> If 0 is written to ADCS during A/D conversion, A/D conversion is immediately stopped, and a timer trigger wait
<7> When 0 is written to ADTMD while A/D conversion operation is stopped (ADCS = 0), the software trigger mode is
Note Leave at least enough time for A/D conversion to finish between each generation of the timer trigger signal.
Remark 78K0R/LF3:
A/D conversion
Timer trigger
register 1 (ADM1) to 1.
set to 1 and A/D conversion of the voltage applied to the analog input pin specified using the analog input
channel specification register (ADS) starts.
register (ADCR, ADCRH), and an interrupt request signal (INTAD) is generated. When one A/D conversion has
been completed, the next A/D conversion operation is immediately started.
restarted from the beginning. At this time, the conversion result immediately before is retained.
stopped and restarted from the beginning. At this time, the conversion result immediately before is retained.
state is entered. At this time, the conversion result immediately before is retained.
set and A/D conversion operation is not started, even if a timer trigger signal is generated.
ADTMD
ADCRH
INTAD
ADCR,
ADCS
78K0R/LG3, 78K0R/LH3:
<1> ADTMD = 1
Figure 10-18. Timer trigger mode (Continuous conversion mode)
<2> Timer trigger generation
Wait
state
<3> A/D conversion
ANIn
is completed
n = 0 to 6, 15, m = 0 to 6, 15
n = 0 to 10, 15, m = 0 to 10, 15
<3> A/D conversion
ANIn
ANIn
is completed
Conversion operation under
execution is stopped, and
restarted from the beginning
Note
ANIn
<4> Rewriting ADS
ANIn
ANIm
<3> A/D conversion
is completed
Conversion operation under
execution is stopped, and
restarted from the beginning
<5> Timer trigger generation
CHAPTER 10 A/D CONVERTER
ANIm
ANIm
ANIm
<6> ADCS = 0
<7> ADTMD = 0
Wait
state
Conversion operation
under execution is
stopped
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