UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 340

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UPD78F1506GF-GAT-AX

Manufacturer Part Number
UPD78F1506GF-GAT-AX
Description
MCU 16BIT 78K0R/LX3 128-LQFP
Manufacturer
Renesas Electronics America
Series
78K0R/Lx3r
Datasheet

Specifications of UPD78F1506GF-GAT-AX

Core Processor
78K/0R
Core Size
16-Bit
Speed
20MHz
Connectivity
3-Wire SIO, I²C, LIN, UART/USART
Peripherals
DMA, LCD, LVD, POR, PWM, WDT
Number Of I /o
78
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Figure 6-64. Example of Set Contents of Registers When One-Shot Pulse Output Function Is Used (Master Channel)
Remarks 1.
TMRmn
TOMm
TOEm
TOLm
TOm
(a) Timer mode register mn (TMRmn)
(b) Timer output register m (TOm)
(c) Timer output enable register m (TOEm)
(d) Timer output level register m (TOLm)
(e) Timer output mode register m (TOMm)
TOMmn
TOEmn
CKSmn
TOLmn
2.
3.
TOmn
Bit n
Bit n
Bit n
Bit n
1/0
15
0
0
0
0
78K0R/LF3:
• m = 0, n = 0, 2, 6, p = n+1, TO00 to TO04, TO07, TI00 to TI04, and TI07 pins
78K0R/LG3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
78K0R/LH3:
• m = 0, n = 0, 2, 4, 6, p = n+1, TO00 to TO07, TI00 to TI07 pins
• m = 1, n = 0, 2, p = n+1, TO10 to TO13, TI10 to TI13 pins
Operation clock selection
14
0: Selects CKm0 as operation clock of channels n.
1: Selects CKm1 as operation clock of channels n.
0
0: Outputs 0 from TOmn.
0: Stops the TOmn output operation by counting operation.
0: Cleared to 0 when TOMmn = 0 (toggle mode).
0: Sets toggle mode.
13
0
CCSmn
12
0
Count clock selection
TERmn
MAS
11
0: Selects operation clock.
1
Slave/master selection
STSmn2
10
1: Channel 1 is set as master channel.
0
STSmn1
9
0
Start trigger selection
STSmn0
000B: Selects the software trigger start.
001B: Selects the TImn pin input valid edge.
8
1
CISmn1
1/0
7
CISmn0
1/0
6
Selection of TImn pin input edge
00B: Detects falling edge.
01B: Detects rising edge.
10B: Detects both edges.
11B: Setting prohibited
Operation mode of channel n
100B: One-count mode
5
0
CHAPTER 6 TIMER ARRAY UNIT
4
0
Start trigger during operation
MDmn3
0: Trigger input is invalid.
3
1
MDmn2
2
0
MDmn1
1
0
MDmn0
0
0
340

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