UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 743

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

<R>
<R>
78K0R/Lx3
18.6 Cautions on Using DMA Controller
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(1) Priority of DMA
(2) DMA response time
During DMA transfer, a request from the other DMA channel is held pending even if generated. The pending
DMA transfer is started after the ongoing DMA transfer is completed. If two DMA requests are generated at the
same time, however, DMA channel 0 takes priority over DMA channel 1.
If a DMA request and an interrupt request are generated at the same time, the DMA transfer takes precedence,
and then interrupt servicing is executed.
The response time of DMA transfer is as follows.
Note The maximum time necessary to execute an instruction from internal RAM is 16 clock cycles.
Cautions 1. The above response time does not include the two clock cycles required for a DMA
Remark
Response time
2. When executing a DMA pending instruction (see 18.6 (4)), the maximum response
3. Do not specify successive transfer triggers for a channel within a period equal to the
1 clock: 1/f
transfer.
time is extended by the execution time of that instruction to be held pending.
maximum response time plus one clock cycle, because they might be ignored.
Table 17-2. Response Time of DMA Transfer
CLK
(f
CLK
: CPU clock)
3 clocks
Minimum Time
10 clocks
CHAPTER 18 DMA CONTROLLER
Maximum Time
Note
743