UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 815

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
24.4 Operation of Low-Voltage Detector
(1) Used as reset (LVIMD = 1)
(2) Used as interrupt (LVIMD = 0)
more than or less than the detection level can be checked by reading the low-voltage detection flag (LVIF: bit 0 of LVIM).
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The low-voltage detector can be used in the following two modes.
While the low-voltage detector is operating, whether the supply voltage or the input voltage from an external input pin is
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
• If LVISEL = 0, compares the supply voltage (V
• If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and detection voltage (V
Remark LVIMD: Bit 1 of low-voltage detection register (LVIM)
when V
an internal reset signal when EXLVI < V
Remark The low-voltage detector (LVI) can be set to ON by an option byte by default. If it is set to ON to raise
(V
±0.1 V
≥ V
Note
DD
EXLVI
< V
Note
DD
This is a preliminary value and subject to change.
LVISEL: Bit 2 of LVIM
), generates an interrupt signal (INTLVI).
LVI
). When EXLVI drops lower than V
< V
the power supply from the POC detection voltage (V
signal is generated when the supply voltage (V
that, the internal reset signal is generated when the supply voltage (V
V ±0.1 V
) or when V
LVI
, and releases internal reset when V
Note
).
DD
becomes V
LVI
or higher (V
EXLVI
, and releases internal reset when EXLVI ≥ V
EXLVI
DD
DD
(EXLVI < V
) and detection voltage (V
) and detection voltage (V
DD
DD
≥ V
≥ V
LVI
LVI
DD
), generates an interrupt signal (INTLVI).
EXLVI
.
) < detection voltage (V
CHAPTER 24 LOW-VOLTAGE DETECTOR
) or when EXLVI becomes V
POR
= 1.61 V (TYP.)) or lower, the internal reset
LVI
LVI
), generates an internal reset signal
). When V
DD
) < detection voltage (V
LVI
= 2.07 V ±0.2 V
EXLVI
DD
drops lower than V
.
EXLVI
or higher (EXLVI
EXLVI
EXLVI
), generates
Note
LVI
= 1.21 V
). After
= 2.07
815
LVI