UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 614

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
15.5.13 Wakeup function
extension code have been received.
addresses do not match.
addresses are transmitted due to the possibility that an arbitration loss may change the master device (which has
generated a start condition) to a slave device.
wakeup function, and this determines whether interrupt requests are enabled or disabled.
clock. An interrupt request signal (INTIICA) is also generated when a local address and extension code have been
received. Operation returns to normal operation by using an instruction to clear (0) the WUP bit after this interrupt has
been generated.
address match.
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
The I
This function makes processing more efficient by preventing unnecessary INTIICA signal from occurring when
When a start condition is detected, wakeup standby mode is set. This wakeup standby mode is in effect while
However, when a stop condition is detected, bit 4 (SPIE) of IICA control register 0 (IICCTL0) is set regardless of the
To use the wakeup function in the STOP mode, set WUP to 1. Addresses can be received regardless of the operation
Figure 15-22 shows the flow for setting WUP = 1 and Figure 15-23 shows the flow for setting WUP = 0 upon an
2
C bus slave function is a function that generates an interrupt request signal (INTIICA) when a local address and
Figure 15-22. Flow When Setting WUP = 1
MSTS = STD = EXC = COI =0?
STOP instruction execution
WUP = 1
START
Wait
Yes
Waits for 3 clocks.
No
CHAPTER 15 SERIAL INTERFACE IICA
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