UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 240

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(2) Example of setting procedure when using the external main system clock
(3) Example of setting procedure when using high-speed system clock as CPU/peripheral hardware clock
<1> Setting P121/X1 and P122/X2/EXCLK pins (CMC register)
<2> Controlling external main system clock input (CSC register)
Cautions 1. The CMC register can be written only once after reset release, by an 8-bit memory
<1> Setting high-speed system clock oscillation
<2> Setting the high-speed system clock as the source clock of the CPU/peripheral hardware clock and setting
Remark For setting of the P123/XT1 and P124/XT2 pins, see 5.6.3 (1) Example of setting procedure
When MSTOP is cleared to 0, the input of the external main system clock is enabled.
(See 5.6.1 (1) Example of setting procedure when oscillating the X1 clock and (2) Example of setting
procedure when using the external main system clock.)
Note The setting of <1> is not necessary when high-speed system clock is already operating.
the division ratio of the set clock (CKC register)
Note Setting is prohibited when f
EXCLK
MCM0
2. Set the external main system clock after the supply voltage has reached the operable voltage
1
1
manipulation instruction.
OSCSELS bits, see 5.6.3 Example of controlling subsystem clock.
of the clock to be used (see CHAPTER 31 ELECTRICAL SPECIFICATIONS).
Therefore, it is necessary to also set the value of the OSCSELS bits at the same time. For
when oscillating the subsystem clock.
OSCSEL
MDIV2
1
0
0
0
0
1
1
MDIV1
0
0
0
0
1
1
0
0
MX
OSCSELS
< 4 MHz.
MDIV0
0/1
0
1
0
1
0
1
Note
f
f
f
f
f
f
MX
MX
MX
MX
MX
MX
/2
/2
/2
/2
/2
0
0
2
3
4
5 Note
Selection of CPU/Peripheral
AMPHS1
Hardware Clock (f
0/1
CHAPTER 5 CLOCK GENERATOR
AMPHS0
0/1
CLK
)
AMPH
0/1
240