UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 656

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
(3) Data ~ data ~ Stop condition
Notes 1. Write data to IICA, not setting the WREL bit, in order to cancel a wait state during master transmission.
(communication status)
(communication status)
(8 or 9 clock wait)
(8 or 9 clock wait)
(wait cancellation)
(wait cancellation)
(transmit/receive)
(transmit/receive)
(ACK detection)
(ACK detection)
Master side
(ST detection)
(SP detection)
(ACK control)
(ACK control)
Slave side
(SP trigger)
SDA0 (bus)
(ST trigger)
SCL0 (bus)
(clock line)
Bus line
(interrupt)
(data line)
(interrupt)
2. Make sure that the time between the rise of the SCL0 pin signal and the generation of the stop condition
3. To cancel slave wait, write “FFH” to IICA or set the WREL bit.
INTIICA
INTIICA
WTIM
MSTS
MSTS
WTIM
WREL
WREL
ACKD
ACKE
ACKD
ACKE
TRC
STD
SPD
TRC
IICA
STT
SPT
IICA
(When 9-Clock Wait Is Selected for Master, 9-Clock Wait Is Selected for Slave) (3/4)
after a stop condition has been issued is at least 4.0
μ
s when specifying fast mode.
D
H
H
L
L
15
<7>
L
H
H
L
L
: Wait state by master device
: Wait state by slave device
: Wait state by master and slave devices
0
Figure 15-32. Example of Master to Slave Communication
ACK
Note 1
<9>
<8>
<10>
D
16
Note 3
7
D
16
6
D
16
5
D
16
4
Stop condition
D
16
μ
3
s when specifying standard mode and at least 0.6
CHAPTER 15 SERIAL INTERFACE IICA
D
16
2
D
16
1
D
<11>
16
0
<12>
ACK
<13>
<14>
Note 2
Note 3
<15>
656