UPD78F1506GF-GAT-AX Renesas Electronics America, UPD78F1506GF-GAT-AX Datasheet - Page 984

• Manufacturer Part Number: UPD78F1506GF-GAT-AX
• Description: MCU 16BIT 78K0R/LX3 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: 78K0R/Lx3r

Specifications of UPD78F1506GF-GAT-AX

• Core Processor: 78K/0R
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: 3-Wire SIO, I²C, LIN, UART/USART
• Peripherals: DMA, LCD, LVD, POR, PWM, WDT
• Number Of I /o: 78
• Program Memory Size: 64KB (64K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

78K0R/Lx3
R01UH0004EJ0401 Rev.4.01
Jul 2, 2010
Serial
interface
IICA
Function
IICA: IICA shift
register
PER0:
Peripheral
enable register 0
IICCTL0: IICA
control register 0
IICS: IICA status
register
IICF: IICA flag
register
Setting IICWL
and IICWH on
slave side
Canceling wait
When STCEN
(bit 1 of IICA flag
register (IICF)) =
0
When STCEN =
1
Details of
Function
Do not write data to IICA during data transfer.
Write or read IICA only during the wait period. Accessing IICA in a communication
state other than during the wait period is prohibited. When the device serves as the
master, however, IICA can be written only once after the communication trigger bit
(STT) is set to 1.
When communication is reserved, write data to IICA after the interrupt triggered by a
stop condition is detected.
When setting serial interface IICA, be sure to set IICAEN to 1 first. If IICAEN = 0,
writing to a control register of serial interface IICA is ignored, and, even if the register
is read, only the default value is read.
If the operation of I
SDA0 line is at low level, and DFC of the IICCTL1 register is 1, a start condition will
be inadvertently detected immediately. Immediately after enabling I
(IICE = 1), set LREL (1) by using a 1-bit memory manipulation instruction.
When bit 3 (TRC) of the IICA status register (IICS) is set to 1, WREL is set to 1
during the ninth clock and wait is canceled, after which TRC is cleared and the SDA0
line is set to high impedance. Release the wait performed while the TRC bit is 1
(transmission status) by writing to the IICA shift register.
Reading the IICS register while the address match wakeup function is enabled (WUP
= 1) in STOP mode is prohibited. When the WUP bit is changed from 1 to 0 (wakeup
operation is stopped), regardless of the INTIICA interrupt request, the change in
status is not reflected until the next start condition or stop condition is detected. To
use the wakeup function, therefore, enable (SPIE = 1) the interrupt generated by
detecting a stop condition and read the IICS register after the interrupt has been
detected.
Write to STCEN only when the operation is stopped (IICE = 0).
As the bus release status (IICBSY = 0) is recognized regardless of the actual bus
status when STCEN = 1, when generating the first start condition (STT = 1), it is
necessary to verify that no third party communications are in progress in order to
prevent such communications from being destroyed.
Write to IICRSV only when the operation is stopped (IICE = 0).
Note the minimum f
minimum f
the mode.
Fast mode:
Standard mode:
If a processing to cancel a wait state executed when WUP (bit 7 of IICA control
register 1 (IICCTL1)) = 1, the wait state will not be canceled.
Immediately after I
(IICBSY = 1) is recognized regardless of the actual bus status. When changing from
a mode in which no stop condition has been detected to a master device
communication mode, first generate a stop condition to release the bus, then perform
master device communication.
When using multiple masters, it is not possible to perform master device
communication when the bus has not been released (when a stop condition has not
been detected).
Use the following sequence for generating a stop condition.
<1> Set IICA control register 1 (IICCTL1).
<2> Set bit 7 (IICE) of IICA control register 0 (IICCTL0) to 1.
<3> Set bit 0 (SPT) of IICCTL0 to 1.
Immediately after I
(IICBSY = 0) is recognized regardless of the actual bus status. To generate the first
start condition (STT = 1), it is necessary to confirm that the bus has been released,
so as to not disturb other communications.
CLK
operation frequency for serial interface IICA is determined according to
2
2
C operation is enabled (IICE = 1), the bus communication status
f
f
2
C is enabled (IICE = 1) when the SCL0 line is at high level, the
CLK
CLK
C operation is enabled (IICE = 1), the bus released status
CLK
= 3.5 MHz (MIN.)
= 1 MHz (MIN.)
operation frequency when setting the transfer clock. The
Cautions
APPENDIX C LIST OF CAUTIONS
2
C to operate
p.586
p.586
p.586
p.589
p.590
p.593
p.594
p.597
p.597
p.597
p.602
p.609
p.621
p.621
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